Lines Matching refs:instr
368 Register Assembler::GetRtReg(Instr instr) {
369 return Register::from_code((instr & kRtFieldMask) >> kRtShift);
372 Register Assembler::GetRsReg(Instr instr) {
373 return Register::from_code((instr & kRsFieldMask) >> kRsShift);
376 Register Assembler::GetRdReg(Instr instr) {
377 return Register::from_code((instr & kRdFieldMask) >> kRdShift);
380 uint32_t Assembler::GetRt(Instr instr) {
381 return (instr & kRtFieldMask) >> kRtShift;
384 uint32_t Assembler::GetRtField(Instr instr) { return instr & kRtFieldMask; }
386 uint32_t Assembler::GetRs(Instr instr) {
387 return (instr & kRsFieldMask) >> kRsShift;
390 uint32_t Assembler::GetRsField(Instr instr) { return instr & kRsFieldMask; }
392 uint32_t Assembler::GetRd(Instr instr) {
393 return (instr & kRdFieldMask) >> kRdShift;
396 uint32_t Assembler::GetRdField(Instr instr) { return instr & kRdFieldMask; }
398 uint32_t Assembler::GetSa(Instr instr) {
399 return (instr & kSaFieldMask) >> kSaShift;
402 uint32_t Assembler::GetSaField(Instr instr) { return instr & kSaFieldMask; }
404 uint32_t Assembler::GetOpcodeField(Instr instr) { return instr & kOpcodeMask; }
406 uint32_t Assembler::GetFunction(Instr instr) {
407 return (instr & kFunctionFieldMask) >> kFunctionShift;
410 uint32_t Assembler::GetFunctionField(Instr instr) {
411 return instr & kFunctionFieldMask;
414 uint32_t Assembler::GetImmediate16(Instr instr) { return instr & kImm16Mask; }
416 uint32_t Assembler::GetLabelConst(Instr instr) { return instr & ~kImm16Mask; }
418 bool Assembler::IsPop(Instr instr) {
419 return (instr & ~kRtMask) == kPopRegPattern;
422 bool Assembler::IsPush(Instr instr) {
423 return (instr & ~kRtMask) == kPushRegPattern;
426 bool Assembler::IsSwRegFpOffset(Instr instr) {
427 return ((instr & kLwSwInstrTypeMask) == kSwRegFpOffsetPattern);
430 bool Assembler::IsLwRegFpOffset(Instr instr) {
431 return ((instr & kLwSwInstrTypeMask) == kLwRegFpOffsetPattern);
434 bool Assembler::IsSwRegFpNegOffset(Instr instr) {
435 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
439 bool Assembler::IsLwRegFpNegOffset(Instr instr) {
440 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
463 bool Assembler::IsMsaBranch(Instr instr) {
464 uint32_t opcode = GetOpcodeField(instr);
465 uint32_t rs_field = GetRsField(instr);
487 bool Assembler::IsBranch(Instr instr) {
488 uint32_t opcode = GetOpcodeField(instr);
489 uint32_t rt_field = GetRtField(instr);
490 uint32_t rs_field = GetRsField(instr);
499 (opcode == COP1 && rs_field == BC1NEZ) || IsMsaBranch(instr);
511 bool Assembler::IsBc(Instr instr) {
512 uint32_t opcode = GetOpcodeField(instr);
517 bool Assembler::IsNal(Instr instr) {
518 uint32_t opcode = GetOpcodeField(instr);
519 uint32_t rt_field = GetRtField(instr);
520 uint32_t rs_field = GetRsField(instr);
524 bool Assembler::IsBzc(Instr instr) {
525 uint32_t opcode = GetOpcodeField(instr);
527 return (opcode == POP66 && GetRsField(instr) != 0) ||
528 (opcode == POP76 && GetRsField(instr) != 0);
531 bool Assembler::IsEmittedConstant(Instr instr) {
532 uint32_t label_constant = GetLabelConst(instr);
536 bool Assembler::IsBeq(Instr instr) { return GetOpcodeField(instr) == BEQ; }
538 bool Assembler::IsBne(Instr instr) { return GetOpcodeField(instr) == BNE; }
540 bool Assembler::IsBeqzc(Instr instr) {
541 uint32_t opcode = GetOpcodeField(instr);
542 return opcode == POP66 && GetRsField(instr) != 0;
545 bool Assembler::IsBnezc(Instr instr) {
546 uint32_t opcode = GetOpcodeField(instr);
547 return opcode == POP76 && GetRsField(instr) != 0;
550 bool Assembler::IsBeqc(Instr instr) {
551 uint32_t opcode = GetOpcodeField(instr);
552 uint32_t rs = GetRsField(instr);
553 uint32_t rt = GetRtField(instr);
557 bool Assembler::IsBnec(Instr instr) {
558 uint32_t opcode = GetOpcodeField(instr);
559 uint32_t rs = GetRsField(instr);
560 uint32_t rt = GetRtField(instr);
564 bool Assembler::IsJicOrJialc(Instr instr) {
565 uint32_t opcode = GetOpcodeField(instr);
566 uint32_t rs = GetRsField(instr);
570 bool Assembler::IsJump(Instr instr) {
571 uint32_t opcode = GetOpcodeField(instr);
572 uint32_t rt_field = GetRtField(instr);
573 uint32_t rd_field = GetRdField(instr);
574 uint32_t function_field = GetFunctionField(instr);
582 bool Assembler::IsJ(Instr instr) {
583 uint32_t opcode = GetOpcodeField(instr);
588 bool Assembler::IsJal(Instr instr) { return GetOpcodeField(instr) == JAL; }
590 bool Assembler::IsJr(Instr instr) {
592 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR;
594 return GetOpcodeField(instr) == SPECIAL && GetRdField(instr) == 0 &&
595 GetFunctionField(instr) == JALR;
599 bool Assembler::IsJalr(Instr instr) {
600 return GetOpcodeField(instr) == SPECIAL && GetRdField(instr) != 0 &&
601 GetFunctionField(instr) == JALR;
604 bool Assembler::IsLui(Instr instr) {
605 uint32_t opcode = GetOpcodeField(instr);
610 bool Assembler::IsOri(Instr instr) {
611 uint32_t opcode = GetOpcodeField(instr);
616 bool Assembler::IsAddu(Instr instr, Register rd, Register rs, Register rt) {
617 uint32_t opcode = GetOpcodeField(instr);
618 uint32_t rd_field = GetRd(instr);
619 uint32_t rs_field = GetRs(instr);
620 uint32_t rt_field = GetRt(instr);
621 uint32_t sa_field = GetSaField(instr);
625 uint32_t function_field = GetFunction(instr);
630 bool Assembler::IsMov(Instr instr, Register rd, Register rs) {
631 uint32_t opcode = GetOpcodeField(instr);
632 uint32_t rd_field = GetRd(instr);
633 uint32_t rs_field = GetRs(instr);
634 uint32_t rt_field = GetRt(instr);
637 uint32_t function_field = GetFunctionField(instr);
644 bool Assembler::IsNop(Instr instr, unsigned int type) {
647 uint32_t opcode = GetOpcodeField(instr);
648 uint32_t function = GetFunctionField(instr);
649 uint32_t rt = GetRt(instr);
650 uint32_t rd = GetRd(instr);
651 uint32_t sa = GetSa(instr);
666 int32_t Assembler::GetBranchOffset(Instr instr) {
667 DCHECK(IsBranch(instr));
668 return (static_cast<int16_t>(instr & kImm16Mask)) << 2;
671 bool Assembler::IsLw(Instr instr) {
672 return (static_cast<uint32_t>(instr & kOpcodeMask) == LW);
675 int16_t Assembler::GetLwOffset(Instr instr) {
676 DCHECK(IsLw(instr));
677 return ((instr & kImm16Mask));
680 Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {
681 DCHECK(IsLw(instr));
684 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask) |
690 bool Assembler::IsSw(Instr instr) {
691 return (static_cast<uint32_t>(instr & kOpcodeMask) == SW);
694 Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {
695 DCHECK(IsSw(instr));
696 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
699 bool Assembler::IsAddImmediate(Instr instr) {
700 return ((instr & kOpcodeMask) == ADDIU);
703 Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {
704 DCHECK(IsAddImmediate(instr));
705 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
708 bool Assembler::IsAndImmediate(Instr instr) {
709 return GetOpcodeField(instr) == ANDI;
712 static Assembler::OffsetSize OffsetSizeInBits(Instr instr) {
714 if (Assembler::IsBc(instr)) {
716 } else if (Assembler::IsBzc(instr)) {
723 static inline int32_t AddBranchOffset(int pos, Instr instr) {
724 int bits = OffsetSizeInBits(instr);
730 int32_t imm = ((instr & mask) << bits) >> (bits - 2);
812 Instr instr = instr_at(pos);
814 if (instr == 0) {
818 int delta = static_cast<int>(instr_address - instr);
823 if ((instr & ~kImm16Mask) == 0) {
825 if (instr == 0) {
828 int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
833 DCHECK(IsBranch(instr) || IsLui(instr) || IsMov(instr, t8, ra));
834 if (IsBranch(instr)) {
835 return AddBranchOffset(pos, instr);
836 } else if (IsMov(instr, t8, ra)) {
847 DCHECK(IsLui(instr));
883 Instr instr) {
884 int32_t bits = OffsetSizeInBits(instr);
890 instr &= ~mask;
893 return instr | (imm & mask);
898 Instr instr = instr_at(pos);
905 if ((instr & ~kImm16Mask) == 0) {
913 DCHECK(IsBranch(instr) || IsLui(instr) || IsMov(instr, t8, ra));
914 if (IsBranch(instr)) {
915 instr = SetBranchOffset(pos, target_pos, instr);
916 instr_at_put(pos, instr);
917 } else if (IsMov(instr, t8, ra)) {
954 DCHECK(IsLui(instr));
1015 Instr instr = instr_at(l.pos());
1016 if ((instr & ~kImm16Mask) == 0) {
1019 PrintF("%d\n", instr);
1045 Instr instr = instr_at(fixup_pos);
1049 if (IsBranch(instr)) {
1050 int branch_offset = BranchOffset(instr);
1104 int Assembler::BranchOffset(Instr instr) {
1109 uint32_t opcode = GetOpcodeField(instr);
1120 if (GetRsField(instr) != 0) bits = OffsetSize::kOffset21;
1142 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1144 emit(instr);
1151 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1153 emit(instr);
1160 Instr instr = opcode | fmt | (ft.code() << kFtShift) |
1162 emit(instr);
1169 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
1171 emit(instr);
1178 Instr instr = opcode | fmt | (rt.code() << kRtShift) |
1180 emit(instr);
1186 Instr instr =
1188 emit(instr);
1197 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1199 emit(instr, is_compact_branch);
1207 Instr instr = opcode | (base.code() << kBaseShift) | (rt.code() << kRtShift) |
1210 emit(instr);
1217 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
1218 emit(instr, is_compact_branch);
1225 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
1227 emit(instr, is_compact_branch);
1233 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1234 emit(instr, is_compact_branch);
1240 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1241 emit(instr);
1247 Instr instr = opcode | (offset26 & kImm26Mask);
1248 emit(instr, is_compact_branch);
1254 Instr instr = opcode | address;
1255 emit(instr);
1264 Instr instr = MSA | operation | ((imm8 & kImm8Mask) << kWtShift) |
1266 emit(instr);
1278 Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) |
1280 emit(instr);
1287 Instr instr = MSA | operation | df | (m << kWtShift) |
1289 emit(instr);
1296 Instr instr = MSA | operation | df | ((imm10 & kImm10Mask) << kWsShift) |
1298 emit(instr);
1306 Instr instr = MSA | operation | df | (t.code() << kWtShift) |
1308 emit(instr);
1316 Instr instr = MSA | operation | df | (n << kWtShift) |
1319 emit(instr);
1327 Instr instr = MSA | operation | (df << 21) | (wt.code() << kWtShift) |
1329 emit(instr);
1336 Instr instr = MSA | operation | (wt.code() << kWtShift) |
1339 emit(instr);
1346 Instr instr = MSA | operation | ((s10 & kImm10Mask) << kWtShift) |
1348 emit(instr);
1355 Instr instr = MSA | MSA_2R_FORMAT | operation | df | (ws.code() << kWsShift) |
1357 emit(instr);
1364 Instr instr = MSA | MSA_2RF_FORMAT | operation | df |
1367 emit(instr);
1375 Instr instr =
1377 emit(instr);
1919 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
1921 emit(instr);
1928 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1930 emit(instr);
1937 Instr instr = SPECIAL | rs.code() << kRsShift | rt.code() << kRtShift |
1939 emit(instr);
2240 Instr instr =
2242 emit(instr);
2247 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift | rt.code() << kRtShift |
2249 emit(instr);
2254 Instr instr =
2256 emit(instr);
2261 Instr instr = SPECIAL | TLTU | rs.code() << kRsShift | rt.code() << kRtShift |
2263 emit(instr);
2268 Instr instr =
2270 emit(instr);
2275 Instr instr =
2277 emit(instr);
2339 // Clz instr requires same GPR number in 'rd' and 'rt' fields.
2348 // Ins instr has 'rt' field as dest, and two uint5: msb, lsb.
2355 // Ext instr has 'rt' field as dest, and two uint5: msb, lsb.
2368 Instr instr =
2370 emit(instr);
2875 Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift |
2877 emit(instr);
2893 Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask);
2894 emit(instr);
2901 Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask);
2902 emit(instr);
2912 Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift | cc << 8 |
2914 emit(instr);
2937 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);
2938 emit(instr);
2945 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);
2946 emit(instr);
3109 Instr instr = MSA | MSA_2R_FORMAT | FILL | MSA_2R_DF_##format | \
3112 emit(instr); \
3403 Instr instr = MSA | MOVE_V | (ws.code() << kWsShift) |
3405 emit(instr);
3411 Instr instr = MSA | CTCMSA | (rs.code() << kWsShift) |
3413 emit(instr);
3419 Instr instr = MSA | CFCMSA | (cs.code() << kWsShift) |
3421 emit(instr);
3457 Instr instr = instr_at(pc);
3468 if (IsLui(instr)) {
3506 Instr instr = instr_at(pc);
3509 if (IsLui(instr)) {
3737 // Patching the address must replace both instr, and flush the i-cache.
3738 // On r6, target address is stored in a lui/jic pair, and both instr have to be
3746 // Check we have the result from a li macro-instruction, using instr pair.