Lines Matching defs:opcode
464 uint32_t opcode = GetOpcodeField(instr);
466 if (opcode == COP1) {
488 uint32_t opcode = GetOpcodeField(instr);
493 opcode == BEQ || opcode == BNE || opcode == BLEZ || opcode == BGTZ ||
494 opcode == BEQL || opcode == BNEL || opcode == BLEZL || opcode == BGTZL ||
495 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
497 (opcode == COP1 && rs_field == BC1) || // Coprocessor branch.
498 (opcode == COP1 && rs_field == BC1EQZ) ||
499 (opcode == COP1 && rs_field == BC1NEZ) || IsMsaBranch(instr);
503 isBranch |= opcode == POP10 || opcode == POP30 || opcode == BC ||
504 opcode == BALC ||
505 (opcode == POP66 && rs_field != 0) || // BEQZC
506 (opcode == POP76 && rs_field != 0); // BNEZC
512 uint32_t opcode = GetOpcodeField(instr);
514 return opcode == BC || opcode == BALC;
518 uint32_t opcode = GetOpcodeField(instr);
521 return opcode == REGIMM && rt_field == BLTZAL && rs_field == 0;
525 uint32_t opcode = GetOpcodeField(instr);
527 return (opcode == POP66 && GetRsField(instr) != 0) ||
528 (opcode == POP76 && GetRsField(instr) != 0);
541 uint32_t opcode = GetOpcodeField(instr);
542 return opcode == POP66 && GetRsField(instr) != 0;
546 uint32_t opcode = GetOpcodeField(instr);
547 return opcode == POP76 && GetRsField(instr) != 0;
551 uint32_t opcode = GetOpcodeField(instr);
554 return opcode == POP10 && rs != 0 && rs < rt; // && rt != 0
558 uint32_t opcode = GetOpcodeField(instr);
561 return opcode == POP30 && rs != 0 && rs < rt; // && rt != 0
565 uint32_t opcode = GetOpcodeField(instr);
567 return (opcode == POP66 || opcode == POP76) && rs == 0;
571 uint32_t opcode = GetOpcodeField(instr);
576 return opcode == J || opcode == JAL ||
577 (opcode == SPECIAL && rt_field == 0 &&
583 uint32_t opcode = GetOpcodeField(instr);
585 return opcode == J;
605 uint32_t opcode = GetOpcodeField(instr);
607 return opcode == LUI;
611 uint32_t opcode = GetOpcodeField(instr);
613 return opcode == ORI;
617 uint32_t opcode = GetOpcodeField(instr);
626 return opcode == SPECIAL && sa_field == 0 && function_field == ADDU &&
631 uint32_t opcode = GetOpcodeField(instr);
639 bool res = opcode == SPECIAL && function_field == OR && rd_field == rd_reg &&
647 uint32_t opcode = GetOpcodeField(instr);
659 bool ret = (opcode == SPECIAL && function == SLL &&
1109 uint32_t opcode = GetOpcodeField(instr);
1110 switch (opcode) {
1138 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt,
1142 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1147 void Assembler::GenInstrRegister(Opcode opcode, Register rs, Register rt,
1151 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1156 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt,
1160 Instr instr = opcode | fmt | (ft.code() << kFtShift) |
1165 void Assembler::GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft,
1169 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
1174 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt,
1178 Instr instr = opcode | fmt | (rt.code() << kRtShift) |
1183 void Assembler::GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt,
1187 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
1193 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, Register rt,
1197 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
1202 void Assembler::GenInstrImmediate(Opcode opcode, Register base, Register rt,
1207 Instr instr = opcode | (base.code() << kBaseShift) | (rt.code() << kRtShift) |
1213 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF,
1217 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
1221 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft,
1225 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
1230 void Assembler::GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21,
1233 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1237 void Assembler::GenInstrImmediate(Opcode opcode, Register rs,
1240 Instr instr = opcode | (rs.code() << kRsShift) | (offset21 & kImm21Mask);
1244 void Assembler::GenInstrImmediate(Opcode opcode, int32_t offset26,
1247 Instr instr = opcode | (offset26 & kImm26Mask);
1251 void Assembler::GenInstrJump(Opcode opcode, uint32_t address) {
1254 Instr instr = opcode | address;
2175 // This instruction uses same opcode as 'lui'. The difference in encoding is
2963 #define MSA_BRANCH(name, opcode) \
2965 GenInstrMsaBranch(opcode, wt, offset); \
2982 #define MSA_LD_ST(name, opcode) \
2987 GenInstrMsaMI10(opcode, source.offset(), source.rm(), wd); \
2993 GenInstrMsaMI10(opcode, 0, scratch, wd); \
3028 #define MSA_I5_FORMAT(name, opcode, format) \
3031 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \
3034 #define MSA_I5(name, opcode) \
3035 MSA_I5_FORMAT(name, opcode, b) \
3036 MSA_I5_FORMAT(name, opcode, h) \
3037 MSA_I5_FORMAT(name, opcode, w) \
3038 MSA_I5_FORMAT(name, opcode, d)
3057 #define MSA_I8(name, opcode) \
3059 GenInstrMsaI8(opcode, imm8, ws, wd); \
3075 #define MSA_VEC(name, opcode) \
3077 GenInstrMsaVec(opcode, wt, ws, wd); \
3089 #define MSA_2R_FORMAT(name, opcode, format) \
3091 GenInstrMsa2R(opcode, MSA_2R_DF_##format, ws, wd); \
3094 #define MSA_2R(name, opcode) \
3095 MSA_2R_FORMAT(name, opcode, b) \
3096 MSA_2R_FORMAT(name, opcode, h) \
3097 MSA_2R_FORMAT(name, opcode, w) \
3098 MSA_2R_FORMAT(name, opcode, d)
3138 #define MSA_2RF_FORMAT(name, opcode, format) \
3140 GenInstrMsa2RF(opcode, MSA_2RF_DF_##format, ws, wd); \
3143 #define MSA_2RF(name, opcode) \
3144 MSA_2RF_FORMAT(name, opcode, w) \
3145 MSA_2RF_FORMAT(name, opcode, d)
3215 #define MSA_3R_FORMAT(name, opcode, format) \
3218 GenInstrMsa3R<MSARegister>(opcode, MSA_3R_DF_##format, wt, ws, wd); \
3221 #define MSA_3R_FORMAT_SLD_SPLAT(name, opcode, format) \
3224 GenInstrMsa3R<Register>(opcode, MSA_3R_DF_##format, rt, ws, wd); \
3227 #define MSA_3R(name, opcode) \
3228 MSA_3R_FORMAT(name, opcode, b) \
3229 MSA_3R_FORMAT(name, opcode, h) \
3230 MSA_3R_FORMAT(name, opcode, w) \
3231 MSA_3R_FORMAT(name, opcode, d)
3233 #define MSA_3R_SLD_SPLAT(name, opcode) \
3234 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, b) \
3235 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, h) \
3236 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, w) \
3237 MSA_3R_FORMAT_SLD_SPLAT(name, opcode, d)
3294 #define MSA_3RF_FORMAT(name, opcode, df, df_c) \
3297 GenInstrMsa3RF(opcode, df_c, wt, ws, wd); \
3300 #define MSA_3RF_1(name, opcode) \
3301 MSA_3RF_FORMAT(name, opcode, w, 0) \
3302 MSA_3RF_FORMAT(name, opcode, d, 1)
3304 #define MSA_3RF_2(name, opcode) \
3305 MSA_3RF_FORMAT(name, opcode, h, 0) \
3306 MSA_3RF_FORMAT(name, opcode, w, 1)
3438 #define MSA_BIT_FORMAT(name, opcode, format) \
3441 GenInstrMsaBit(opcode, BIT_DF_##format, m, ws, wd); \
3444 #define MSA_BIT(name, opcode) \
3445 MSA_BIT_FORMAT(name, opcode, b) \
3446 MSA_BIT_FORMAT(name, opcode, h) \
3447 MSA_BIT_FORMAT(name, opcode, w) \
3448 MSA_BIT_FORMAT(name, opcode, d)