Lines Matching refs:rk
41 static inline bool IsZero(const Operand& rk) {
42 if (rk.is_reg()) {
43 return rk.rm() == zero_reg;
45 return rk.immediate() == 0;
343 void TurboAssembler::Add_w(Register rd, Register rj, const Operand& rk) {
344 if (rk.is_reg()) {
345 add_w(rd, rj, rk.rm());
347 if (is_int12(rk.immediate()) && !MustUseReg(rk.rmode())) {
348 addi_w(rd, rj, static_cast<int32_t>(rk.immediate()));
354 li(scratch, rk);
360 void TurboAssembler::Add_d(Register rd, Register rj, const Operand& rk) {
361 if (rk.is_reg()) {
362 add_d(rd, rj, rk.rm());
364 if (is_int12(rk.immediate()) && !MustUseReg(rk.rmode())) {
365 addi_d(rd, rj, static_cast<int32_t>(rk.immediate()));
371 li(scratch, rk);
377 void TurboAssembler::Sub_w(Register rd, Register rj, const Operand& rk) {
378 if (rk.is_reg()) {
379 sub_w(rd, rj, rk.rm());
381 DCHECK(is_int32(rk.immediate()));
382 if (is_int12(-rk.immediate()) && !MustUseReg(rk.rmode())) {
384 addi_w(rd, rj, static_cast<int32_t>(-rk.immediate()));
389 if (-rk.immediate() >> 12 == 0 && !MustUseReg(rk.rmode())) {
391 li(scratch, -rk.immediate());
395 li(scratch, rk);
402 void TurboAssembler::Sub_d(Register rd, Register rj, const Operand& rk) {
403 if (rk.is_reg()) {
404 sub_d(rd, rj, rk.rm());
405 } else if (is_int12(-rk.immediate()) && !MustUseReg(rk.rmode())) {
407 addi_d(rd, rj, static_cast<int32_t>(-rk.immediate()));
410 int li_count = InstrCountForLi64Bit(rk.immediate());
411 int li_neg_count = InstrCountForLi64Bit(-rk.immediate());
412 if (li_neg_count < li_count && !MustUseReg(rk.rmode())) {
414 DCHECK(rk.immediate() != std::numeric_limits<int32_t>::min());
417 li(scratch, Operand(-rk.immediate()));
423 li(scratch, rk);
429 void TurboAssembler::Mul_w(Register rd, Register rj, const Operand& rk) {
430 if (rk.is_reg()) {
431 mul_w(rd, rj, rk.rm());
437 li(scratch, rk);
442 void TurboAssembler::Mulh_w(Register rd, Register rj, const Operand& rk) {
443 if (rk.is_reg()) {
444 mulh_w(rd, rj, rk.rm());
450 li(scratch, rk);
455 void TurboAssembler::Mulh_wu(Register rd, Register rj, const Operand& rk) {
456 if (rk.is_reg()) {
457 mulh_wu(rd, rj, rk.rm());
463 li(scratch, rk);
468 void TurboAssembler::Mul_d(Register rd, Register rj, const Operand& rk) {
469 if (rk.is_reg()) {
470 mul_d(rd, rj, rk.rm());
476 li(scratch, rk);
481 void TurboAssembler::Mulh_d(Register rd, Register rj, const Operand& rk) {
482 if (rk.is_reg()) {
483 mulh_d(rd, rj, rk.rm());
489 li(scratch, rk);
494 void TurboAssembler::Div_w(Register rd, Register rj, const Operand& rk) {
495 if (rk.is_reg()) {
496 div_w(rd, rj, rk.rm());
502 li(scratch, rk);
507 void TurboAssembler::Mod_w(Register rd, Register rj, const Operand& rk) {
508 if (rk.is_reg()) {
509 mod_w(rd, rj, rk.rm());
515 li(scratch, rk);
520 void TurboAssembler::Mod_wu(Register rd, Register rj, const Operand& rk) {
521 if (rk.is_reg()) {
522 mod_wu(rd, rj, rk.rm());
528 li(scratch, rk);
533 void TurboAssembler::Div_d(Register rd, Register rj, const Operand& rk) {
534 if (rk.is_reg()) {
535 div_d(rd, rj, rk.rm());
541 li(scratch, rk);
546 void TurboAssembler::Div_wu(Register rd, Register rj, const Operand& rk) {
547 if (rk.is_reg()) {
548 div_wu(rd, rj, rk.rm());
554 li(scratch, rk);
559 void TurboAssembler::Div_du(Register rd, Register rj, const Operand& rk) {
560 if (rk.is_reg()) {
561 div_du(rd, rj, rk.rm());
567 li(scratch, rk);
572 void TurboAssembler::Mod_d(Register rd, Register rj, const Operand& rk) {
573 if (rk.is_reg()) {
574 mod_d(rd, rj, rk.rm());
580 li(scratch, rk);
585 void TurboAssembler::Mod_du(Register rd, Register rj, const Operand& rk) {
586 if (rk.is_reg()) {
587 mod_du(rd, rj, rk.rm());
593 li(scratch, rk);
598 void TurboAssembler::And(Register rd, Register rj, const Operand& rk) {
599 if (rk.is_reg()) {
600 and_(rd, rj, rk.rm());
602 if (is_uint12(rk.immediate()) && !MustUseReg(rk.rmode())) {
603 andi(rd, rj, static_cast<int32_t>(rk.immediate()));
609 li(scratch, rk);
615 void TurboAssembler::Or(Register rd, Register rj, const Operand& rk) {
616 if (rk.is_reg()) {
617 or_(rd, rj, rk.rm());
619 if (is_uint12(rk.immediate()) && !MustUseReg(rk.rmode())) {
620 ori(rd, rj, static_cast<int32_t>(rk.immediate()));
626 li(scratch, rk);
632 void TurboAssembler::Xor(Register rd, Register rj, const Operand& rk) {
633 if (rk.is_reg()) {
634 xor_(rd, rj, rk.rm());
636 if (is_uint12(rk.immediate()) && !MustUseReg(rk.rmode())) {
637 xori(rd, rj, static_cast<int32_t>(rk.immediate()));
643 li(scratch, rk);
649 void TurboAssembler::Nor(Register rd, Register rj, const Operand& rk) {
650 if (rk.is_reg()) {
651 nor(rd, rj, rk.rm());
657 li(scratch, rk);
662 void TurboAssembler::Andn(Register rd, Register rj, const Operand& rk) {
663 if (rk.is_reg()) {
664 andn(rd, rj, rk.rm());
670 li(scratch, rk);
675 void TurboAssembler::Orn(Register rd, Register rj, const Operand& rk) {
676 if (rk.is_reg()) {
677 orn(rd, rj, rk.rm());
683 li(scratch, rk);
688 void TurboAssembler::Neg(Register rj, const Operand& rk) {
689 DCHECK(rk.is_reg());
690 sub_d(rj, zero_reg, rk.rm());
693 void TurboAssembler::Slt(Register rd, Register rj, const Operand& rk) {
694 if (rk.is_reg()) {
695 slt(rd, rj, rk.rm());
697 if (is_int12(rk.immediate()) && !MustUseReg(rk.rmode())) {
698 slti(rd, rj, static_cast<int32_t>(rk.immediate()));
705 li(scratch, rk);
711 void TurboAssembler::Sltu(Register rd, Register rj, const Operand& rk) {
712 if (rk.is_reg()) {
713 sltu(rd, rj, rk.rm());
715 if (is_int12(rk.immediate()) && !MustUseReg(rk.rmode())) {
716 sltui(rd, rj, static_cast<int32_t>(rk.immediate()));
723 li(scratch, rk);
729 void TurboAssembler::Sle(Register rd, Register rj, const Operand& rk) {
730 if (rk.is_reg()) {
731 slt(rd, rk.rm(), rj);
738 li(scratch, rk);
744 void TurboAssembler::Sleu(Register rd, Register rj, const Operand& rk) {
745 if (rk.is_reg()) {
746 sltu(rd, rk.rm(), rj);
753 li(scratch, rk);
759 void TurboAssembler::Sge(Register rd, Register rj, const Operand& rk) {
760 Slt(rd, rj, rk);
764 void TurboAssembler::Sgeu(Register rd, Register rj, const Operand& rk) {
765 Sltu(rd, rj, rk);
769 void TurboAssembler::Sgt(Register rd, Register rj, const Operand& rk) {
770 if (rk.is_reg()) {
771 slt(rd, rk.rm(), rj);
778 li(scratch, rk);
783 void TurboAssembler::Sgtu(Register rd, Register rj, const Operand& rk) {
784 if (rk.is_reg()) {
785 sltu(rd, rk.rm(), rj);
792 li(scratch, rk);
797 void TurboAssembler::Rotr_w(Register rd, Register rj, const Operand& rk) {
798 if (rk.is_reg()) {
799 rotr_w(rd, rj, rk.rm());
801 int64_t ror_value = rk.immediate() % 32;
809 void TurboAssembler::Rotr_d(Register rd, Register rj, const Operand& rk) {
810 if (rk.is_reg()) {
811 rotr_d(rd, rj, rk.rm());
813 int64_t dror_value = rk.immediate() % 64;
819 void TurboAssembler::Alsl_w(Register rd, Register rj, Register rk, uint8_t sa,
823 alsl_w(rd, rj, rk, sa);
825 Register tmp = rd == rk ? scratch : rd;
826 DCHECK(tmp != rk);
828 add_w(rd, rk, tmp);
832 void TurboAssembler::Alsl_d(Register rd, Register rj, Register rk, uint8_t sa,
836 alsl_d(rd, rj, rk, sa);
838 Register tmp = rd == rk ? scratch : rd;
839 DCHECK(tmp != rk);
841 add_d(rd, rk, tmp);
1396 void TurboAssembler::Bstrpick_w(Register rk, Register rj, uint16_t msbw,
1401 bstrpick_w(rk, rj, msbw, lsbw);
1404 void TurboAssembler::Bstrpick_d(Register rk, Register rj, uint16_t msbw,
1409 bstrpick_d(rk, rj, msbw, lsbw);
1904 void TurboAssembler::Movz(Register rd, Register rj, Register rk) {
1907 masknez(scratch, rj, rk);
1908 maskeqz(rd, rd, rk);
1912 void TurboAssembler::Movn(Register rd, Register rj, Register rk) {
1915 maskeqz(scratch, rj, rk);
1916 masknez(rd, rd, rk);
1921 const Operand& rk, Condition cond) {
1929 if (rk.is_reg()) {
1930 LoadZeroIfConditionZero(rd, rk.rm());
1931 } else if (rk.immediate() == 0) {
1934 } else if (IsZero(rk)) {
1937 Sub_d(t7, rj, rk);
1943 if (rk.is_reg()) {
1944 LoadZeroIfConditionNotZero(rd, rk.rm());
1945 } else if (rk.immediate() != 0) {
1948 } else if (IsZero(rk)) {
1951 Sub_d(t7, rj, rk);
1958 Sgt(t7, rj, rk);
1962 Sge(t7, rj, rk);
1964 // rj >= rk
1967 Slt(t7, rj, rk);
1969 // rj < rk
1972 Sle(t7, rj, rk);
1974 // rj <= rk
1979 Sgtu(t7, rj, rk);
1981 // rj > rk
1985 Sgeu(t7, rj, rk);
1987 // rj >= rk
1990 Sltu(t7, rj, rk);
1992 // rj < rk
1995 Sleu(t7, rj, rk);
1997 // rj <= rk
2198 #define BRANCH_ARGS_CHECK(cond, rj, rk) \
2199 DCHECK((cond == cc_always && rj == zero_reg && rk.rm() == zero_reg) || \
2200 (cond != cc_always && (rj != zero_reg || rk.rm() != zero_reg)))
2212 const Operand& rk, bool need_link) {
2214 BRANCH_ARGS_CHECK(cond, rj, rk);
2215 if (!BranchShortOrFallback(L, cond, rj, rk, need_link)) {
2219 BranchShort(&skip, neg_cond, rj, rk, need_link);
2231 BranchShort(&skip, neg_cond, rj, rk, need_link);
2238 BranchShort(L, cond, rj, rk, need_link);
2255 Register TurboAssembler::GetRkAsRegisterHelper(const Operand& rk,
2258 if (rk.is_reg()) {
2259 r2 = rk.rm();
2262 li(r2, rk);
2269 Register rj, const Operand& rk,
2293 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2300 } else if (IsZero(rk)) {
2309 Register sc = GetRkAsRegisterHelper(rk, scratch);
2315 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2322 } else if (IsZero(rk)) {
2331 Register sc = GetRkAsRegisterHelper(rk, scratch);
2339 // rj > rk
2340 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2342 } else if (IsZero(rk)) {
2350 Register sc = GetRkAsRegisterHelper(rk, scratch);
2357 // rj >= rk
2358 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2363 } else if (IsZero(rk)) {
2371 Register sc = GetRkAsRegisterHelper(rk, scratch);
2378 // rj < rk
2379 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2381 } else if (IsZero(rk)) {
2389 Register sc = GetRkAsRegisterHelper(rk, scratch);
2396 // rj <= rk
2397 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2402 } else if (IsZero(rk)) {
2410 Register sc = GetRkAsRegisterHelper(rk, scratch);
2419 // rj > rk
2420 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2422 } else if (IsZero(rk)) {
2430 Register sc = GetRkAsRegisterHelper(rk, scratch);
2437 // rj >= rk
2438 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2443 } else if (IsZero(rk)) {
2451 Register sc = GetRkAsRegisterHelper(rk, scratch);
2458 // rj < rk
2459 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2461 } else if (IsZero(rk)) {
2466 Register sc = GetRkAsRegisterHelper(rk, scratch);
2473 // rj <= rk
2474 if (rk.is_reg() && rj.code() == rk.rm().code()) {
2479 } else if (IsZero(rk)) {
2486 Register sc = GetRkAsRegisterHelper(rk, scratch);
2500 const Operand& rk, bool need_link) {
2501 BRANCH_ARGS_CHECK(cond, rj, rk);
2502 bool result = BranchShortOrFallback(L, cond, rj, rk, need_link);
2531 const Operand& rk) {
2536 BRANCH_ARGS_CHECK(cond, rj, rk);
2538 Branch(&skip, NegateCondition(cond), rj, rk);
2545 Condition cond, Register rj, const Operand& rk) {
2548 Branch(&skip, NegateCondition(cond), rj, rk);
2559 Register rj, const Operand& rk) {
2561 Jump(static_cast<intptr_t>(target), rmode, cond, rj, rk);
2565 Condition cond, Register rj, const Operand& rk) {
2571 BranchShort(&skip, NegateCondition(cond), rj, rk);
2590 Jump(t7, cc_always, rj, rk);
2598 Jump(t7, cc_always, rj, rk);
2604 Jump(static_cast<intptr_t>(code.address()), rmode, cc_always, rj, rk);
2615 const Operand& rk) {
2620 BRANCH_ARGS_CHECK(cond, rj, rk);
2622 Branch(&skip, NegateCondition(cond), rj, rk);
2644 Register rj, const Operand& rk) {
2648 BranchShort(&skip, NegateCondition(cond), rj, rk);
2658 Call(t7, cc_always, rj, rk);
2664 Condition cond, Register rj, const Operand& rk) {
2668 BranchShort(&skip, NegateCondition(cond), rj, rk);
2691 Call(t7, cond, rj, rk);
2699 Call(t7, cond, rj, rk);
2707 Call(code.address(), rmode, cc_always, rj, rk);
2827 void TurboAssembler::Ret(Condition cond, Register rj, const Operand& rk) {
2828 Jump(ra, cond, rj, rk);
3383 Operand rk) {
3384 if (FLAG_debug_code) Check(cc, reason, rs, rk);
3388 Operand rk) {
3390 Branch(&L, cc, rj, rk);