Lines Matching defs:opcode
308 uint32_t opcode = (instr >> 26) << 26;
310 bool isBranch = opcode == BEQZ || opcode == BNEZ || opcode == BCZ ||
311 opcode == B || opcode == BL || opcode == BEQ ||
312 opcode == BNE || opcode == BLT || opcode == BGE ||
313 opcode == BLTU || opcode == BGEU;
318 uint32_t opcode = (instr >> 26) << 26;
320 bool isBranch = opcode == B || opcode == BL;
325 uint32_t opcode = (instr >> 26) << 26;
327 bool isBranch = opcode == BEQZ || opcode == BNEZ || opcode == BCZ;
338 uint32_t opcode = (instr >> 26) << 26;
340 return opcode == JIRL;
344 uint32_t opcode = (instr >> 25) << 25;
345 return opcode == LU12I_W;
349 uint32_t opcode = (instr >> 22) << 22;
350 return opcode == ORI;
354 uint32_t opcode = (instr >> 25) << 25;
355 return opcode == LU32I_D;
359 uint32_t opcode = (instr >> 22) << 22;
360 return opcode == LU52I_D;
643 uint32_t opcode = (instr >> 26) << 26;
644 switch (opcode) {
678 void Assembler::GenB(Opcode opcode, Register rj, int32_t si21) {
680 DCHECK((BEQZ == opcode || BNEZ == opcode) && is_int21(si21) && rj.is_valid());
681 Instr instr = opcode | (si21 & kImm16Mask) << kRkShift |
686 void Assembler::GenB(Opcode opcode, CFRegister cj, int32_t si21, bool isEq) {
688 DCHECK(BCZ == opcode && is_int21(si21));
691 Instr instr = opcode | (si21 & kImm16Mask) << kRkShift | (sc << kRjShift) |
696 void Assembler::GenB(Opcode opcode, int32_t si26) {
698 DCHECK((B == opcode || BL == opcode) && is_int26(si26));
700 opcode | ((si26 & kImm16Mask) << kRkShift) | ((si26 & kImm26Mask) >> 16);
704 void Assembler::GenBJ(Opcode opcode, Register rj, Register rd, int32_t si16) {
707 Instr instr = opcode | ((si16 & kImm16Mask) << kRkShift) |
712 void Assembler::GenCmp(Opcode opcode, FPUCondition cond, FPURegister fk,
714 DCHECK(opcode == FCMP_COND_S || opcode == FCMP_COND_D);
715 Instr instr = opcode | cond << kCondShift | (fk.code() << kFkShift) |
720 void Assembler::GenSel(Opcode opcode, CFRegister ca, FPURegister fk,
722 DCHECK((opcode == FSEL));
723 Instr instr = opcode | ca << kCondShift | (fk.code() << kFkShift) |
728 void Assembler::GenRegister(Opcode opcode, Register rj, Register rd,
732 instr = opcode | (rj.code() << kRjShift) | rd.code();
736 void Assembler::GenRegister(Opcode opcode, FPURegister fj, FPURegister fd) {
737 Instr instr = opcode | (fj.code() << kFjShift) | fd.code();
741 void Assembler::GenRegister(Opcode opcode, Register rj, FPURegister fd) {
742 DCHECK((opcode == MOVGR2FR_W) || (opcode == MOVGR2FR_D) ||
743 (opcode == MOVGR2FRH_W));
744 Instr instr = opcode | (rj.code() << kRjShift) | fd.code();
748 void Assembler::GenRegister(Opcode opcode, FPURegister fj, Register rd) {
749 DCHECK((opcode == MOVFR2GR_S) || (opcode == MOVFR2GR_D) ||
750 (opcode == MOVFRH2GR_S));
751 Instr instr = opcode | (fj.code() << kFjShift) | rd.code();
755 void Assembler::GenRegister(Opcode opcode, Register rj, FPUControlRegister fd) {
756 DCHECK((opcode == MOVGR2FCSR));
757 Instr instr = opcode | (rj.code() << kRjShift) | fd.code();
761 void Assembler::GenRegister(Opcode opcode, FPUControlRegister fj, Register rd) {
762 DCHECK((opcode == MOVFCSR2GR));
763 Instr instr = opcode | (fj.code() << kFjShift) | rd.code();
767 void Assembler::GenRegister(Opcode opcode, FPURegister fj, CFRegister cd) {
768 DCHECK((opcode == MOVFR2CF));
769 Instr instr = opcode | (fj.code() << kFjShift) | cd;
773 void Assembler::GenRegister(Opcode opcode, CFRegister cj, FPURegister fd) {
774 DCHECK((opcode == MOVCF2FR));
775 Instr instr = opcode | cj << kFjShift | fd.code();
779 void Assembler::GenRegister(Opcode opcode, Register rj, CFRegister cd) {
780 DCHECK((opcode == MOVGR2CF));
781 Instr instr = opcode | (rj.code() << kRjShift) | cd;
785 void Assembler::GenRegister(Opcode opcode, CFRegister cj, Register rd) {
786 DCHECK((opcode == MOVCF2GR));
787 Instr instr = opcode | cj << kFjShift | rd.code();
791 void Assembler::GenRegister(Opcode opcode, Register rk, Register rj,
794 opcode | (rk.code() << kRkShift) | (rj.code() << kRjShift) | rd.code();
798 void Assembler::GenRegister(Opcode opcode, FPURegister fk, FPURegister fj,
801 opcode | (fk.code() << kFkShift) | (fj.code() << kFjShift) | fd.code();
805 void Assembler::GenRegister(Opcode opcode, FPURegister fa, FPURegister fk,
807 Instr instr = opcode | (fa.code() << kFaShift) | (fk.code() << kFkShift) |
812 void Assembler::GenRegister(Opcode opcode, Register rk, Register rj,
815 opcode | (rk.code() << kRkShift) | (rj.code() << kRjShift) | fd.code();
819 void Assembler::GenImm(Opcode opcode, int32_t bit3, Register rk, Register rj,
822 Instr instr = opcode | (bit3 & 0x7) << kSaShift | (rk.code() << kRkShift) |
827 void Assembler::GenImm(Opcode opcode, int32_t bit6m, int32_t bit6l, Register rj,
830 Instr instr = opcode | (bit6m & 0x3f) << 16 | (bit6l & 0x3f) << kRkShift |
835 void Assembler::GenImm(Opcode opcode, int32_t bit20, Register rd) {
837 Instr instr = opcode | (bit20 & 0xfffff) << kRjShift | rd.code();
841 void Assembler::GenImm(Opcode opcode, int32_t bit15) {
843 Instr instr = opcode | (bit15 & 0x7fff);
847 void Assembler::GenImm(Opcode opcode, int32_t value, Register rj, Register rd,
859 Instr instr = opcode | imm << kRkShift | (rj.code() << kRjShift) | rd.code();
863 void Assembler::GenImm(Opcode opcode, int32_t bit12, Register rj,
866 Instr instr = opcode | ((bit12 & kImm12Mask) << kRkShift) |