Lines Matching defs:dst
202 void Move(Register dst, Smi src);
203 void Move(Register dst, MemOperand src);
204 void Move(Register dst, Register src);
556 inline void SmiUntag(Register dst, Register src);
557 inline void SmiUntag(Register dst, const MemOperand& src);
560 inline void SmiTag(Register dst, Register src);
619 // instruction. Returns true for success, and updates the contents of dst.
621 bool TryOneInstrMoveImmediate(const Register& dst, int64_t imm);
700 // the stack offset specified by dst. The offsets and count are expressed in
701 // slot-sized units. Offset dst must be less than src, or the gap between
705 void CopySlots(int dst, Register src, Register slot_count);
706 void CopySlots(Register dst, Register src, Register slot_count);
709 // in register dst. There are three modes for this function:
710 // 1) Address dst must be less than src, or the gap between them must be
713 // 2) Address src must be less than dst, or the gap between them must be
715 // undpredictable. In this mode, src and dst specify the last (highest)
718 // The case where src == dst is not supported.
726 void CopyDoubleWords(Register dst, Register src, Register count,
730 // stack pointer, and write it to dst. Positive slot_offsets are at addresses
732 void SlotAddress(Register dst, int slot_offset);
733 void SlotAddress(Register dst, Register slot_offset);
884 // Move an immediate into register dst, and return an Operand object for use
886 // dst is not necessarily equal to imm; it may have had a shifting operation
889 Operand MoveImmediateForShiftedOp(const Register& dst, int64_t imm,
920 void LoadMap(Register dst, Register object);
1112 // Peek at a value on the stack, and put it in 'dst'. The offset is in bytes.
1116 // value. 'dst' must be lr in this case.
1118 void Peek(const CPURegister& dst, const Operand& offset);
1145 void CanonicalizeNaN(const VRegister& dst, const VRegister& src);
1191 void St1(const VRegister& vt, const MemOperand& dst) {
1193 st1(vt, dst);
1195 void St1(const VRegister& vt, const VRegister& vt2, const MemOperand& dst) {
1197 st1(vt, vt2, dst);
1200 const MemOperand& dst) {
1202 st1(vt, vt2, vt3, dst);
1205 const VRegister& vt4, const MemOperand& dst) {
1207 st1(vt, vt2, vt3, vt4, dst);
1209 void St1(const VRegister& vt, int lane, const MemOperand& dst) {
1211 st1(vt, lane, dst);
1391 void SmiUntagField(Register dst, const MemOperand& src);
1431 void PopcntHelper(Register dst, Register src);
1432 void I64x2BitMask(Register dst, VRegister src);
1433 void I64x2AllTrue(Register dst, VRegister src);
1626 const MemOperand& dst);
1701 void St2(const VRegister& vt, const VRegister& vt2, const MemOperand& dst) {
1703 st2(vt, vt2, dst);
1706 const MemOperand& dst) {
1708 st3(vt, vt2, vt3, dst);
1711 const VRegister& vt4, const MemOperand& dst) {
1713 st4(vt, vt2, vt3, vt4, dst);
1716 const MemOperand& dst) {
1718 st2(vt, vt2, lane, dst);
1721 int lane, const MemOperand& dst) {
1723 st3(vt, vt2, vt3, lane, dst);
1726 const VRegister& vt4, int lane, const MemOperand& dst) {
1728 st4(vt, vt2, vt3, vt4, lane, dst);
1830 void DecodeField(Register dst, Register src) {
1833 Ubfx(dst, src, shift, setbits);
2029 void LoadGlobalProxy(Register dst);
2081 void LoadNativeContextSlot(Register dst, int index);