Lines Matching defs:operand
156 const Operand& operand, LogicalOp op) {
160 if (operand.NeedsRelocation(this)) {
162 Ldr(temp, operand.immediate());
165 } else if (operand.IsImmediate()) {
166 int64_t immediate = operand.ImmediateValue();
244 } else if (operand.IsExtendedRegister()) {
245 DCHECK(operand.reg().SizeInBits() <= rd.SizeInBits());
248 DCHECK_LE(operand.shift_amount(), 4);
249 DCHECK(operand.reg().Is64Bits() ||
250 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
252 EmitExtendShift(temp, operand.reg(), operand.extend(),
253 operand.shift_amount());
257 // The operand can be encoded in the instruction.
258 DCHECK(operand.IsShiftedRegister());
259 Logical(rd, rn, operand, op);
339 void TurboAssembler::Mov(const Register& rd, const Operand& operand,
349 if (operand.NeedsRelocation(this)) {
354 if (operand.ImmediateRMode() == RelocInfo::EXTERNAL_REFERENCE) {
355 Address addr = static_cast<Address>(operand.ImmediateValue());
359 } else if (RelocInfo::IsEmbeddedObjectMode(operand.ImmediateRMode())) {
361 reinterpret_cast<Address*>(operand.ImmediateValue()));
368 Ldr(dst, operand);
369 } else if (operand.IsImmediate()) {
371 Mov(dst, operand.ImmediateValue());
372 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) {
376 EmitShift(dst, operand.reg(), operand.shift(), operand.shift_amount());
377 } else if (operand.IsExtendedRegister()) {
380 EmitExtendShift(dst, operand.reg(), operand.extend(),
381 operand.shift_amount());
391 // If sp is an operand, add #0 is emitted, otherwise, orr #0.
392 if (rd != operand.reg() ||
394 Assembler::mov(rd, operand.reg());
579 void TurboAssembler::Mvn(const Register& rd, const Operand& operand) {
582 if (operand.NeedsRelocation(this)) {
583 Ldr(rd, operand.immediate());
586 } else if (operand.IsImmediate()) {
588 Mov(rd, ~operand.ImmediateValue());
590 } else if (operand.IsExtendedRegister()) {
593 EmitExtendShift(rd, operand.reg(), operand.extend(),
594 operand.shift_amount());
598 mvn(rd, operand);
632 const Operand& operand,
636 if (operand.NeedsRelocation(this)) {
639 Ldr(temp, operand.immediate());
642 } else if ((operand.IsShiftedRegister() && (operand.shift_amount() == 0)) ||
643 (operand.IsImmediate() &&
644 IsImmConditionalCompare(operand.ImmediateValue()))) {
645 // The immediate can be encoded in the instruction, or the operand is an
647 ConditionalCompare(rn, operand, nzcv, cond, op);
650 // The operand isn't directly supported by the instruction: perform the
654 Mov(temp, operand);
660 const Operand& operand, Condition cond) {
664 if (operand.IsImmediate()) {
667 int64_t imm = operand.ImmediateValue();
681 } else if (operand.IsShiftedRegister() && (operand.shift_amount() == 0)) {
683 csel(rd, rn, operand.reg(), cond);
688 Mov(temp, operand);
751 // return a new leftward-shifting operand.
755 // return a new rightward-shifting operand.
766 const Operand& operand, FlagsUpdate S,
768 if (operand.IsZero() && rd == rn && rd.Is64Bits() && rn.Is64Bits() &&
769 !operand.NeedsRelocation(this) && (S == LeaveFlags)) {
774 if (operand.NeedsRelocation(this)) {
777 Ldr(temp, operand.immediate());
779 } else if ((operand.IsImmediate() &&
780 !IsImmAddSub(operand.ImmediateValue())) ||
781 (rn.IsZero() && !operand.IsShiftedRegister()) ||
782 (operand.IsShiftedRegister() && (operand.shift() == ROR))) {
785 if (operand.IsImmediate()) {
800 MoveImmediateForShiftedOp(temp, operand.ImmediateValue(), mode);
803 Mov(temp, operand);
807 AddSub(rd, rn, operand, S, op);
813 const Operand& operand, FlagsUpdate S,
818 if (operand.NeedsRelocation(this)) {
820 Ldr(temp, operand.immediate());
823 } else if (operand.IsImmediate() ||
824 (operand.IsShiftedRegister() && (operand.shift() == ROR))) {
827 Mov(temp, operand);
830 } else if (operand.IsShiftedRegister() && (operand.shift_amount() != 0)) {
832 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
833 DCHECK(operand.shift() != ROR);
834 DCHECK(is_uintn(operand.shift_amount(), rd.SizeInBits() == kXRegSizeInBits
838 EmitShift(temp, operand.reg(), operand.shift(), operand.shift_amount());
841 } else if (operand.IsExtendedRegister()) {
843 DCHECK(operand.reg().SizeInBits() <= rd.SizeInBits());
846 DCHECK_LE(operand.shift_amount(), 4);
847 DCHECK(operand.reg().Is64Bits() ||
848 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
850 EmitExtendShift(temp, operand.reg(), operand.extend(),
851 operand.shift_amount());
856 AddSubWithCarry(rd, rn, operand, S, op);
1985 // Untagging is folded into the indexing operand below.