Lines Matching refs:rn
24 void TurboAssembler::And(const Register& rd, const Register& rn,
28 LogicalMacro(rd, rn, operand, AND);
31 void TurboAssembler::Ands(const Register& rd, const Register& rn,
35 LogicalMacro(rd, rn, operand, ANDS);
38 void TurboAssembler::Tst(const Register& rn, const Operand& operand) {
40 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS);
43 void TurboAssembler::Bic(const Register& rd, const Register& rn,
47 LogicalMacro(rd, rn, operand, BIC);
50 void MacroAssembler::Bics(const Register& rd, const Register& rn,
54 LogicalMacro(rd, rn, operand, BICS);
57 void TurboAssembler::Orr(const Register& rd, const Register& rn,
61 LogicalMacro(rd, rn, operand, ORR);
64 void TurboAssembler::Orn(const Register& rd, const Register& rn,
68 LogicalMacro(rd, rn, operand, ORN);
71 void TurboAssembler::Eor(const Register& rd, const Register& rn,
75 LogicalMacro(rd, rn, operand, EOR);
78 void TurboAssembler::Eon(const Register& rd, const Register& rn,
82 LogicalMacro(rd, rn, operand, EON);
85 void TurboAssembler::Ccmp(const Register& rn, const Operand& operand,
89 ConditionalCompareMacro(rn, -operand.ImmediateValue(), nzcv, cond, CCMN);
91 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMP);
95 void TurboAssembler::CcmpTagged(const Register& rn, const Operand& operand,
98 Ccmp(rn.W(), operand.ToW(), nzcv, cond);
100 Ccmp(rn, operand, nzcv, cond);
104 void MacroAssembler::Ccmn(const Register& rn, const Operand& operand,
108 ConditionalCompareMacro(rn, -operand.ImmediateValue(), nzcv, cond, CCMP);
110 ConditionalCompareMacro(rn, operand, nzcv, cond, CCMN);
114 void TurboAssembler::Add(const Register& rd, const Register& rn,
119 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, SUB);
121 AddSubMacro(rd, rn, operand, LeaveFlags, ADD);
125 void TurboAssembler::Adds(const Register& rd, const Register& rn,
130 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, SUB);
132 AddSubMacro(rd, rn, operand, SetFlags, ADD);
136 void TurboAssembler::Sub(const Register& rd, const Register& rn,
141 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, ADD);
143 AddSubMacro(rd, rn, operand, LeaveFlags, SUB);
147 void TurboAssembler::Subs(const Register& rd, const Register& rn,
152 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, ADD);
154 AddSubMacro(rd, rn, operand, SetFlags, SUB);
158 void TurboAssembler::Cmn(const Register& rn, const Operand& operand) {
160 Adds(AppropriateZeroRegFor(rn), rn, operand);
163 void TurboAssembler::Cmp(const Register& rn, const Operand& operand) {
165 Subs(AppropriateZeroRegFor(rn), rn, operand);
168 void TurboAssembler::CmpTagged(const Register& rn, const Operand& operand) {
170 Cmp(rn.W(), operand.ToW());
172 Cmp(rn, operand);
191 void TurboAssembler::Adc(const Register& rd, const Register& rn,
195 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, ADC);
198 void MacroAssembler::Adcs(const Register& rd, const Register& rn,
202 AddSubWithCarryMacro(rd, rn, operand, SetFlags, ADC);
205 void MacroAssembler::Sbc(const Register& rd, const Register& rn,
209 AddSubWithCarryMacro(rd, rn, operand, LeaveFlags, SBC);
212 void MacroAssembler::Sbcs(const Register& rd, const Register& rn,
216 AddSubWithCarryMacro(rd, rn, operand, SetFlags, SBC);
257 void TurboAssembler::FN(const Register& rt, const Register& rn) { \
259 OP(rt, rn); \
266 const Register& rn) { \
268 OP(rs, rt, rn); \
273 void TurboAssembler::Asr(const Register& rd, const Register& rn,
277 asr(rd, rn, shift);
280 void TurboAssembler::Asr(const Register& rd, const Register& rn,
284 asrv(rd, rn, rm);
298 void TurboAssembler::Bfi(const Register& rd, const Register& rn, unsigned lsb,
302 bfi(rd, rn, lsb, width);
305 void MacroAssembler::Bfxil(const Register& rd, const Register& rn, unsigned lsb,
309 bfxil(rd, rn, lsb, width);
393 void MacroAssembler::Cinc(const Register& rd, const Register& rn,
398 cinc(rd, rn, cond);
401 void MacroAssembler::Cinv(const Register& rd, const Register& rn,
406 cinv(rd, rn, cond);
409 void TurboAssembler::Cls(const Register& rd, const Register& rn) {
412 cls(rd, rn);
415 void TurboAssembler::Clz(const Register& rd, const Register& rn) {
418 clz(rd, rn);
421 void TurboAssembler::Cneg(const Register& rd, const Register& rn,
426 cneg(rd, rn, cond);
440 void TurboAssembler::CmovX(const Register& rd, const Register& rn,
444 DCHECK(rd.Is64Bits() && rn.Is64Bits());
446 if (rd != rn) {
447 csel(rd, rn, rd, cond);
470 void TurboAssembler::Csinc(const Register& rd, const Register& rn,
475 csinc(rd, rn, rm, cond);
478 void MacroAssembler::Csinv(const Register& rd, const Register& rn,
483 csinv(rd, rn, rm, cond);
486 void MacroAssembler::Csneg(const Register& rd, const Register& rn,
491 csneg(rd, rn, rm, cond);
509 void MacroAssembler::Extr(const Register& rd, const Register& rn,
513 extr(rd, rn, rm, lsb);
657 void TurboAssembler::Fmov(VRegister fd, Register rn) {
659 fmov(fd, rn);
773 void TurboAssembler::Lsl(const Register& rd, const Register& rn,
777 lsl(rd, rn, shift);
780 void TurboAssembler::Lsl(const Register& rd, const Register& rn,
784 lslv(rd, rn, rm);
787 void TurboAssembler::Lsr(const Register& rd, const Register& rn,
791 lsr(rd, rn, shift);
794 void TurboAssembler::Lsr(const Register& rd, const Register& rn,
798 lsrv(rd, rn, rm);
801 void TurboAssembler::Madd(const Register& rd, const Register& rn,
805 madd(rd, rn, rm, ra);
808 void TurboAssembler::Mneg(const Register& rd, const Register& rn,
812 mneg(rd, rn, rm);
832 void TurboAssembler::Msub(const Register& rd, const Register& rn,
836 msub(rd, rn, rm, ra);
839 void TurboAssembler::Mul(const Register& rd, const Register& rn,
843 mul(rd, rn, rm);
846 void TurboAssembler::Rbit(const Register& rd, const Register& rn) {
849 rbit(rd, rn);
852 void TurboAssembler::Rev(const Register& rd, const Register& rn) {
855 rev(rd, rn);
865 void MacroAssembler::Rev(const Register& rd, const Register& rn) {
868 rev(rd, rn);
871 void TurboAssembler::Rev16(const Register& rd, const Register& rn) {
874 rev16(rd, rn);
877 void TurboAssembler::Rev32(const Register& rd, const Register& rn) {
880 rev32(rd, rn);
890 void TurboAssembler::Ror(const Register& rd, const Register& rn,
894 rorv(rd, rn, rm);
897 void MacroAssembler::Sbfiz(const Register& rd, const Register& rn, unsigned lsb,
901 sbfiz(rd, rn, lsb, width);
904 void TurboAssembler::Sbfx(const Register& rd, const Register& rn, unsigned lsb,
908 sbfx(rd, rn, lsb, width);
911 void TurboAssembler::Scvtf(const VRegister& fd, const Register& rn,
914 scvtf(fd, rn, fbits);
917 void TurboAssembler::Sdiv(const Register& rd, const Register& rn,
921 sdiv(rd, rn, rm);
924 void MacroAssembler::Smaddl(const Register& rd, const Register& rn,
928 smaddl(rd, rn, rm, ra);
931 void MacroAssembler::Smsubl(const Register& rd, const Register& rn,
935 smsubl(rd, rn, rm, ra);
938 void TurboAssembler::Smull(const Register& rd, const Register& rn,
942 smull(rd, rn, rm);
945 void MacroAssembler::Smulh(const Register& rd, const Register& rn,
949 smulh(rd, rn, rm);
952 void TurboAssembler::Umull(const Register& rd, const Register& rn,
956 umaddl(rd, rn, rm, xzr);
959 void TurboAssembler::Sxtb(const Register& rd, const Register& rn) {
962 sxtb(rd, rn);
965 void TurboAssembler::Sxth(const Register& rd, const Register& rn) {
968 sxth(rd, rn);
971 void TurboAssembler::Sxtw(const Register& rd, const Register& rn) {
974 sxtw(rd, rn);
977 void TurboAssembler::Ubfiz(const Register& rd, const Register& rn, unsigned lsb,
981 ubfiz(rd, rn, lsb, width);
984 void TurboAssembler::Ubfx(const Register& rd, const Register& rn, unsigned lsb,
988 ubfx(rd, rn, lsb, width);
991 void TurboAssembler::Ucvtf(const VRegister& fd, const Register& rn,
994 ucvtf(fd, rn, fbits);
997 void TurboAssembler::Udiv(const Register& rd, const Register& rn,
1001 udiv(rd, rn, rm);
1004 void MacroAssembler::Umaddl(const Register& rd, const Register& rn,
1008 umaddl(rd, rn, rm, ra);
1011 void MacroAssembler::Umsubl(const Register& rd, const Register& rn,
1015 umsubl(rd, rn, rm, ra);
1018 void TurboAssembler::Uxtb(const Register& rd, const Register& rn) {
1021 uxtb(rd, rn);
1024 void TurboAssembler::Uxth(const Register& rd, const Register& rn) {
1027 uxth(rd, rn);
1030 void TurboAssembler::Uxtw(const Register& rd, const Register& rn) {
1033 uxtw(rd, rn);