Lines Matching refs:vd
1433 void Assembler::NEON3DifferentL(const VRegister& vd, const VRegister& vn,
1436 DCHECK((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) ||
1437 (vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
1438 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
1439 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
1441 if (vd.IsScalar()) {
1447 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
1450 void Assembler::NEON3DifferentW(const VRegister& vd, const VRegister& vn,
1452 DCHECK(AreSameFormat(vd, vn));
1453 DCHECK((vm.Is8B() && vd.Is8H()) || (vm.Is4H() && vd.Is4S()) ||
1454 (vm.Is2S() && vd.Is2D()) || (vm.Is16B() && vd.Is8H()) ||
1455 (vm.Is8H() && vd.Is4S()) || (vm.Is4S() && vd.Is2D()));
1456 Emit(VFormat(vm) | vop | Rm(vm) | Rn(vn) | Rd(vd));
1459 void Assembler::NEON3DifferentHN(const VRegister& vd, const VRegister& vn,
1462 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
1463 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
1464 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
1465 Emit(VFormat(vd) | vop | Rm(vm) | Rn(vn) | Rd(vd));
1507 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
1510 NEON3DifferentL(vd, vn, vm, OP); \
1516 V(addhn, NEON_ADDHN, vd.IsD()) \
1517 V(addhn2, NEON_ADDHN2, vd.IsQ()) \
1518 V(raddhn, NEON_RADDHN, vd.IsD()) \
1519 V(raddhn2, NEON_RADDHN2, vd.IsQ()) \
1520 V(subhn, NEON_SUBHN, vd.IsD()) \
1521 V(subhn2, NEON_SUBHN2, vd.IsQ()) \
1522 V(rsubhn, NEON_RSUBHN, vd.IsD()) \
1523 V(rsubhn2, NEON_RSUBHN2, vd.IsQ())
1526 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
1529 NEON3DifferentHN(vd, vn, vm, OP); \
1534 void Assembler::NEONPerm(const VRegister& vd, const VRegister& vn,
1536 DCHECK(AreSameFormat(vd, vn, vm));
1537 DCHECK(!vd.Is1D());
1538 Emit(VFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
1541 void Assembler::trn1(const VRegister& vd, const VRegister& vn,
1543 NEONPerm(vd, vn, vm, NEON_TRN1);
1546 void Assembler::trn2(const VRegister& vd, const VRegister& vn,
1548 NEONPerm(vd, vn, vm, NEON_TRN2);
1551 void Assembler::uzp1(const VRegister& vd, const VRegister& vn,
1553 NEONPerm(vd, vn, vm, NEON_UZP1);
1556 void Assembler::uzp2(const VRegister& vd, const VRegister& vn,
1558 NEONPerm(vd, vn, vm, NEON_UZP2);
1561 void Assembler::zip1(const VRegister& vd, const VRegister& vn,
1563 NEONPerm(vd, vn, vm, NEON_ZIP1);
1566 void Assembler::zip2(const VRegister& vd, const VRegister& vn,
1568 NEONPerm(vd, vn, vm, NEON_ZIP2);
1571 void Assembler::NEONShiftImmediate(const VRegister& vd, const VRegister& vn,
1573 DCHECK(AreSameFormat(vd, vn));
1579 q = vd.IsD() ? 0 : NEON_Q;
1582 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd));
1585 void Assembler::NEONShiftLeftImmediate(const VRegister& vd, const VRegister& vn,
1589 NEONShiftImmediate(vd, vn, op, (laneSizeInBits + shift) << 16);
1592 void Assembler::NEONShiftRightImmediate(const VRegister& vd,
1597 NEONShiftImmediate(vd, vn, op, ((2 * laneSizeInBits) - shift) << 16);
1600 void Assembler::NEONShiftImmediateL(const VRegister& vd, const VRegister& vn,
1606 DCHECK((vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
1607 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
1608 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
1611 Emit(q | op | immh_immb | Rn(vn) | Rd(vd));
1614 void Assembler::NEONShiftImmediateN(const VRegister& vd, const VRegister& vn,
1617 int laneSizeInBits = vd.LaneSizeInBits();
1622 DCHECK((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
1623 (vd.Is1S() && vn.Is1D()));
1627 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
1628 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
1629 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
1631 q = vd.IsD() ? 0 : NEON_Q;
1633 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd));
1636 void Assembler::shl(const VRegister& vd, const VRegister& vn, int shift) {
1637 DCHECK(vd.IsVector() || vd.Is1D());
1638 NEONShiftLeftImmediate(vd, vn, shift, NEON_SHL);
1641 void Assembler::sli(const VRegister& vd, const VRegister& vn, int shift) {
1642 DCHECK(vd.IsVector() || vd.Is1D());
1643 NEONShiftLeftImmediate(vd, vn, shift, NEON_SLI);
1646 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) {
1647 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHL_imm);
1650 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) {
1651 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHLU);
1654 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) {
1655 NEONShiftLeftImmediate(vd, vn, shift, NEON_UQSHL_imm);
1658 void Assembler::sshll(const VRegister& vd, const VRegister& vn, int shift) {
1660 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
1663 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) {
1665 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
1668 void Assembler::sxtl(const VRegister& vd, const VRegister& vn) {
1669 sshll(vd, vn, 0);
1672 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) {
1673 sshll2(vd, vn, 0);
1676 void Assembler::ushll(const VRegister& vd, const VRegister& vn, int shift) {
1678 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
1681 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) {
1683 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
1686 void Assembler::uxtl(const VRegister& vd, const VRegister& vn) {
1687 ushll(vd, vn, 0);
1690 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) {
1691 ushll2(vd, vn, 0);
1694 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) {
1695 DCHECK(vd.IsVector() || vd.Is1D());
1696 NEONShiftRightImmediate(vd, vn, shift, NEON_SRI);
1699 void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) {
1700 DCHECK(vd.IsVector() || vd.Is1D());
1701 NEONShiftRightImmediate(vd, vn, shift, NEON_SSHR);
1704 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) {
1705 DCHECK(vd.IsVector() || vd.Is1D());
1706 NEONShiftRightImmediate(vd, vn, shift, NEON_USHR);
1709 void Assembler::srshr(const VRegister& vd, const VRegister& vn, int shift) {
1710 DCHECK(vd.IsVector() || vd.Is1D());
1711 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSHR);
1714 void Assembler::urshr(const VRegister& vd, const VRegister& vn, int shift) {
1715 DCHECK(vd.IsVector() || vd.Is1D());
1716 NEONShiftRightImmediate(vd, vn, shift, NEON_URSHR);
1719 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) {
1720 DCHECK(vd.IsVector() || vd.Is1D());
1721 NEONShiftRightImmediate(vd, vn, shift, NEON_SSRA);
1724 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) {
1725 DCHECK(vd.IsVector() || vd.Is1D());
1726 NEONShiftRightImmediate(vd, vn, shift, NEON_USRA);
1729 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) {
1730 DCHECK(vd.IsVector() || vd.Is1D());
1731 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSRA);
1734 void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) {
1735 DCHECK(vd.IsVector() || vd.Is1D());
1736 NEONShiftRightImmediate(vd, vn, shift, NEON_URSRA);
1739 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) {
1740 DCHECK(vn.IsVector() && vd.IsD());
1741 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
1744 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) {
1745 DCHECK(vn.IsVector() && vd.IsQ());
1746 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
1749 void Assembler::rshrn(const VRegister& vd, const VRegister& vn, int shift) {
1750 DCHECK(vn.IsVector() && vd.IsD());
1751 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
1754 void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1755 DCHECK(vn.IsVector() && vd.IsQ());
1756 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
1759 void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) {
1760 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1761 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
1764 void Assembler::sqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1765 DCHECK(vn.IsVector() && vd.IsQ());
1766 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
1769 void Assembler::sqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
1770 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1771 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
1774 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1775 DCHECK(vn.IsVector() && vd.IsQ());
1776 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
1779 void Assembler::sqshrun(const VRegister& vd, const VRegister& vn, int shift) {
1780 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1781 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
1784 void Assembler::sqshrun2(const VRegister& vd, const VRegister& vn, int shift) {
1785 DCHECK(vn.IsVector() && vd.IsQ());
1786 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
1789 void Assembler::sqrshrun(const VRegister& vd, const VRegister& vn, int shift) {
1790 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1791 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
1794 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) {
1795 DCHECK(vn.IsVector() && vd.IsQ());
1796 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
1799 void Assembler::uqshrn(const VRegister& vd, const VRegister& vn, int shift) {
1800 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1801 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
1804 void Assembler::uqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1805 DCHECK(vn.IsVector() && vd.IsQ());
1806 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
1809 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
1810 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1811 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
1814 void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1815 DCHECK(vn.IsVector() && vd.IsQ());
1816 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
1819 void Assembler::uaddw(const VRegister& vd, const VRegister& vn,
1822 NEON3DifferentW(vd, vn, vm, NEON_UADDW);
1825 void Assembler::uaddw2(const VRegister& vd, const VRegister& vn,
1828 NEON3DifferentW(vd, vn, vm, NEON_UADDW2);
1831 void Assembler::saddw(const VRegister& vd, const VRegister& vn,
1834 NEON3DifferentW(vd, vn, vm, NEON_SADDW);
1837 void Assembler::saddw2(const VRegister& vd, const VRegister& vn,
1840 NEON3DifferentW(vd, vn, vm, NEON_SADDW2);
1843 void Assembler::usubw(const VRegister& vd, const VRegister& vn,
1846 NEON3DifferentW(vd, vn, vm, NEON_USUBW);
1849 void Assembler::usubw2(const VRegister& vd, const VRegister& vn,
1852 NEON3DifferentW(vd, vn, vm, NEON_USUBW2);
1855 void Assembler::ssubw(const VRegister& vd, const VRegister& vn,
1858 NEON3DifferentW(vd, vn, vm, NEON_SSUBW);
1861 void Assembler::ssubw2(const VRegister& vd, const VRegister& vn,
1864 NEON3DifferentW(vd, vn, vm, NEON_SSUBW2);
1878 void Assembler::ins(const VRegister& vd, int vd_index, const Register& rn) {
1879 // We support vd arguments of the form vd.VxT() or vd.T(), where x is the
1881 int lane_size = vd.LaneSizeInBytes();
1905 Emit(NEON_INS_GENERAL | ImmNEON5(format, vd_index) | Rn(rn) | Rd(vd));
1938 void Assembler::cls(const VRegister& vd, const VRegister& vn) {
1939 DCHECK(AreSameFormat(vd, vn));
1940 DCHECK(!vd.Is1D() && !vd.Is2D());
1941 Emit(VFormat(vn) | NEON_CLS | Rn(vn) | Rd(vd));
1944 void Assembler::clz(const VRegister& vd, const VRegister& vn) {
1945 DCHECK(AreSameFormat(vd, vn));
1946 DCHECK(!vd.Is1D() && !vd.Is2D());
1947 Emit(VFormat(vn) | NEON_CLZ | Rn(vn) | Rd(vd));
1950 void Assembler::cnt(const VRegister& vd, const VRegister& vn) {
1951 DCHECK(AreSameFormat(vd, vn));
1952 DCHECK(vd.Is8B() || vd.Is16B());
1953 Emit(VFormat(vn) | NEON_CNT | Rn(vn) | Rd(vd));
1956 void Assembler::rev16(const VRegister& vd, const VRegister& vn) {
1957 DCHECK(AreSameFormat(vd, vn));
1958 DCHECK(vd.Is8B() || vd.Is16B());
1959 Emit(VFormat(vn) | NEON_REV16 | Rn(vn) | Rd(vd));
1962 void Assembler::rev32(const VRegister& vd, const VRegister& vn) {
1963 DCHECK(AreSameFormat(vd, vn));
1964 DCHECK(vd.Is8B() || vd.Is16B() || vd.Is4H() || vd.Is8H());
1965 Emit(VFormat(vn) | NEON_REV32 | Rn(vn) | Rd(vd));
1968 void Assembler::rev64(const VRegister& vd, const VRegister& vn) {
1969 DCHECK(AreSameFormat(vd, vn));
1970 DCHECK(!vd.Is1D() && !vd.Is2D());
1971 Emit(VFormat(vn) | NEON_REV64 | Rn(vn) | Rd(vd));
1974 void Assembler::ursqrte(const VRegister& vd, const VRegister& vn) {
1975 DCHECK(AreSameFormat(vd, vn));
1976 DCHECK(vd.Is2S() || vd.Is4S());
1977 Emit(VFormat(vn) | NEON_URSQRTE | Rn(vn) | Rd(vd));
1980 void Assembler::urecpe(const VRegister& vd, const VRegister& vn) {
1981 DCHECK(AreSameFormat(vd, vn));
1982 DCHECK(vd.Is2S() || vd.Is4S());
1983 Emit(VFormat(vn) | NEON_URECPE | Rn(vn) | Rd(vd));
1986 void Assembler::NEONAddlp(const VRegister& vd, const VRegister& vn,
1991 DCHECK((vn.Is8B() && vd.Is4H()) || (vn.Is4H() && vd.Is2S()) ||
1992 (vn.Is2S() && vd.Is1D()) || (vn.Is16B() && vd.Is8H()) ||
1993 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
1994 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
1997 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) {
1998 NEONAddlp(vd, vn, NEON_SADDLP);
2001 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) {
2002 NEONAddlp(vd, vn, NEON_UADDLP);
2005 void Assembler::sadalp(const VRegister& vd, const VRegister& vn) {
2006 NEONAddlp(vd, vn, NEON_SADALP);
2009 void Assembler::uadalp(const VRegister& vd, const VRegister& vn) {
2010 NEONAddlp(vd, vn, NEON_UADALP);
2013 void Assembler::NEONAcrossLanesL(const VRegister& vd, const VRegister& vn,
2015 DCHECK((vn.Is8B() && vd.Is1H()) || (vn.Is16B() && vd.Is1H()) ||
2016 (vn.Is4H() && vd.Is1S()) || (vn.Is8H() && vd.Is1S()) ||
2017 (vn.Is4S() && vd.Is1D()));
2018 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
2021 void Assembler::saddlv(const VRegister& vd, const VRegister& vn) {
2022 NEONAcrossLanesL(vd, vn, NEON_SADDLV);
2025 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) {
2026 NEONAcrossLanesL(vd, vn, NEON_UADDLV);
2029 void Assembler::NEONAcrossLanes(const VRegister& vd, const VRegister& vn,
2031 DCHECK((vn.Is8B() && vd.Is1B()) || (vn.Is16B() && vd.Is1B()) ||
2032 (vn.Is4H() && vd.Is1H()) || (vn.Is8H() && vd.Is1H()) ||
2033 (vn.Is4S() && vd.Is1S()));
2035 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd));
2037 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
2042 V(fmaxv, NEON_FMAXV, vd.Is1S()) \
2043 V(fminv, NEON_FMINV, vd.Is1S()) \
2044 V(fmaxnmv, NEON_FMAXNMV, vd.Is1S()) \
2045 V(fminnmv, NEON_FMINNMV, vd.Is1S()) \
2053 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
2055 NEONAcrossLanes(vd, vn, OP); \
2060 void Assembler::mov(const VRegister& vd, int vd_index, const Register& rn) {
2061 ins(vd, vd_index, rn);
2096 void Assembler::mov(const VRegister& vd, const VRegister& vn, int vn_index) {
2097 DCHECK(vd.IsScalar());
2098 dup(vd, vn, vn_index);
2101 void Assembler::dup(const VRegister& vd, const Register& rn) {
2102 DCHECK(!vd.Is1D());
2103 DCHECK_EQ(vd.Is2D(), rn.IsX());
2104 Instr q = vd.IsD() ? 0 : NEON_Q;
2105 Emit(q | NEON_DUP_GENERAL | ImmNEON5(VFormat(vd), 0) | Rn(rn) | Rd(vd));
2108 void Assembler::ins(const VRegister& vd, int vd_index, const VRegister& vn,
2110 DCHECK(AreSameFormat(vd, vn));
2111 // We support vd arguments of the form vd.VxT() or vd.T(), where x is the
2113 int lane_size = vd.LaneSizeInBytes();
2136 ImmNEON4(format, vn_index) | Rn(vn) | Rd(vd));
2139 void Assembler::NEONTable(const VRegister& vd, const VRegister& vn,
2141 DCHECK(vd.Is16B() || vd.Is8B());
2143 DCHECK(AreSameFormat(vd, vm));
2144 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
2147 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2149 NEONTable(vd, vn, vm, NEON_TBL_1v);
2152 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2157 NEONTable(vd, vn, vm, NEON_TBL_2v);
2160 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2167 NEONTable(vd, vn, vm, NEON_TBL_3v);
2170 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2178 NEONTable(vd, vn, vm, NEON_TBL_4v);
2181 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2183 NEONTable(vd, vn, vm, NEON_TBX_1v);
2186 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2191 NEONTable(vd, vn, vm, NEON_TBX_2v);
2194 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2201 NEONTable(vd, vn, vm, NEON_TBX_3v);
2204 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2212 NEONTable(vd, vn, vm, NEON_TBX_4v);
2215 void Assembler::mov(const VRegister& vd, int vd_index, const VRegister& vn,
2217 ins(vd, vd_index, vn, vn_index);
2614 void Assembler::fmov(const VRegister& vd, double imm) {
2615 if (vd.IsScalar()) {
2616 DCHECK(vd.Is1D());
2617 Emit(FMOV_d_imm | Rd(vd) | ImmFP(imm));
2619 DCHECK(vd.Is2D());
2621 Emit(NEON_Q | op | ImmNEONFP(imm) | NEONCmode(0xF) | Rd(vd));
2625 void Assembler::fmov(const VRegister& vd, float imm) {
2626 if (vd.IsScalar()) {
2627 DCHECK(vd.Is1S());
2628 Emit(FMOV_s_imm | Rd(vd) | ImmFP(imm));
2630 DCHECK(vd.Is2S() || vd.Is4S());
2632 Instr q = vd.Is4S() ? NEON_Q : 0;
2633 Emit(q | op | ImmNEONFP(imm) | NEONCmode(0xF) | Rd(vd));
2643 void Assembler::fmov(const VRegister& vd, const Register& rn) {
2644 DCHECK_EQ(vd.SizeInBits(), rn.SizeInBits());
2645 FPIntegerConvertOp op = vd.Is32Bits() ? FMOV_sw : FMOV_dx;
2646 Emit(op | Rd(vd) | Rn(rn));
2649 void Assembler::fmov(const VRegister& vd, const VRegister& vn) {
2650 DCHECK_EQ(vd.SizeInBits(), vn.SizeInBits());
2651 Emit(FPType(vd) | FMOV | Rd(vd) | Rn(vn));
2654 void Assembler::fmov(const VRegister& vd, int index, const Register& rn) {
2655 DCHECK((index == 1) && vd.Is1D() && rn.IsX());
2657 Emit(FMOV_d1_x | Rd(vd) | Rn(rn));
2686 void Assembler::fnmul(const VRegister& vd, const VRegister& vn,
2688 DCHECK(AreSameSizeAndType(vd, vn, vm));
2689 Instr op = vd.Is1S() ? FNMUL_s : FNMUL_d;
2690 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
2725 void Assembler::NEONFPConvertToInt(const VRegister& vd, const VRegister& vn,
2728 DCHECK((vd.Is1S() && vn.Is1S()) || (vd.Is1D() && vn.Is1D()));
2731 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd));
2734 void Assembler::fcvt(const VRegister& vd, const VRegister& vn) {
2736 if (vd.Is1D()) {
2739 } else if (vd.Is1S()) {
2743 DCHECK(vd.Is1H());
2747 FPDataProcessing1Source(vd, vn, op);
2750 void Assembler::fcvtl(const VRegister& vd, const VRegister& vn) {
2751 DCHECK((vd.Is4S() && vn.Is4H()) || (vd.Is2D() && vn.Is2S()));
2752 Instr format = vd.Is2D() ? (1 << NEONSize_offset) : 0;
2753 Emit(format | NEON_FCVTL | Rn(vn) | Rd(vd));
2756 void Assembler::fcvtl2(const VRegister& vd, const VRegister& vn) {
2757 DCHECK((vd.Is4S() && vn.Is8H()) || (vd.Is2D() && vn.Is4S()));
2758 Instr format = vd.Is2D() ? (1 << NEONSize_offset) : 0;
2759 Emit(NEON_Q | format | NEON_FCVTL | Rn(vn) | Rd(vd));
2762 void Assembler::fcvtn(const VRegister& vd, const VRegister& vn) {
2763 DCHECK((vn.Is4S() && vd.Is4H()) || (vn.Is2D() && vd.Is2S()));
2765 Emit(format | NEON_FCVTN | Rn(vn) | Rd(vd));
2768 void Assembler::fcvtn2(const VRegister& vd, const VRegister& vn) {
2769 DCHECK((vn.Is4S() && vd.Is8H()) || (vn.Is2D() && vd.Is4S()));
2771 Emit(NEON_Q | format | NEON_FCVTN | Rn(vn) | Rd(vd));
2774 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) {
2776 if (vd.IsScalar()) {
2777 DCHECK(vd.Is1S() && vn.Is1D());
2778 Emit(format | NEON_FCVTXN_scalar | Rn(vn) | Rd(vd));
2780 DCHECK(vd.Is2S() && vn.Is2D());
2781 Emit(format | NEON_FCVTXN | Rn(vn) | Rd(vd));
2785 void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) {
2786 DCHECK(vd.Is4S() && vn.Is2D());
2788 Emit(NEON_Q | format | NEON_FCVTXN | Rn(vn) | Rd(vd));
2810 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
2811 NEONFPConvertToInt(vd, vn, VEC_OP); \
2816 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) {
2819 NEONFP2RegMisc(vd, vn, NEON_SCVTF);
2821 DCHECK(vd.Is1D() || vd.Is1S() || vd.Is2D() || vd.Is2S() || vd.Is4S());
2822 NEONShiftRightImmediate(vd, vn, fbits, NEON_SCVTF_imm);
2826 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) {
2829 NEONFP2RegMisc(vd, vn, NEON_UCVTF);
2831 DCHECK(vd.Is1D() || vd.Is1S() || vd.Is2D() || vd.Is2S() || vd.Is4S());
2832 NEONShiftRightImmediate(vd, vn, fbits, NEON_UCVTF_imm);
2836 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) {
2839 Emit(SF(rn) | FPType(vd) | SCVTF | Rn(rn) | Rd(vd));
2841 Emit(SF(rn) | FPType(vd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2842 Rd(vd));
2856 void Assembler::NEON3Same(const VRegister& vd, const VRegister& vn,
2858 DCHECK(AreSameFormat(vd, vn, vm));
2859 DCHECK(vd.IsVector() || !vd.IsQ());
2862 if (vd.IsScalar()) {
2864 format = SFormat(vd);
2866 format = VFormat(vd);
2869 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
2872 void Assembler::NEONFP3Same(const VRegister& vd, const VRegister& vn,
2874 DCHECK(AreSameFormat(vd, vn, vm));
2875 Emit(FPFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
2893 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
2895 if (vd.IsScalar()) { \
2896 DCHECK(vd.Is1S() || vd.Is1D()); \
2899 DCHECK(vd.Is2S() || vd.Is2D() || vd.Is4S()); \
2902 NEONFP2RegMisc(vd, vn, op); \
2907 void Assembler::shll(const VRegister& vd, const VRegister& vn, int shift) {
2908 DCHECK((vd.Is8H() && vn.Is8B() && shift == 8) ||
2909 (vd.Is4S() && vn.Is4H() && shift == 16) ||
2910 (vd.Is2D() && vn.Is2S() && shift == 32));
2912 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd));
2915 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) {
2917 DCHECK((vd.Is8H() && vn.Is16B() && shift == 8) ||
2918 (vd.Is4S() && vn.Is8H() && shift == 16) ||
2919 (vd.Is2D() && vn.Is4S() && shift == 32));
2920 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd));
2923 void Assembler::NEONFP2RegMisc(const VRegister& vd, const VRegister& vn,
2925 DCHECK(AreSameFormat(vd, vn));
2930 if (vd.IsScalar()) {
2931 DCHECK(vd.Is1S() || vd.Is1D());
2934 DCHECK(vd.Is2S() || vd.Is2D() || vd.Is4S());
2937 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd));
2940 void Assembler::fcmeq(const VRegister& vd, const VRegister& vn, double value) {
2941 NEONFP2RegMisc(vd, vn, NEON_FCMEQ_zero, value);
2944 void Assembler::fcmge(const VRegister& vd, const VRegister& vn, double value) {
2945 NEONFP2RegMisc(vd, vn, NEON_FCMGE_zero, value);
2948 void Assembler::fcmgt(const VRegister& vd, const VRegister& vn, double value) {
2949 NEONFP2RegMisc(vd, vn, NEON_FCMGT_zero, value);
2952 void Assembler::fcmle(const VRegister& vd, const VRegister& vn, double value) {
2953 NEONFP2RegMisc(vd, vn, NEON_FCMLE_zero, value);
2956 void Assembler::fcmlt(const VRegister& vd, const VRegister& vn, double value) {
2957 NEONFP2RegMisc(vd, vn, NEON_FCMLT_zero, value);
2960 void Assembler::frecpx(const VRegister& vd, const VRegister& vn) {
2961 DCHECK(vd.IsScalar());
2962 DCHECK(AreSameFormat(vd, vn));
2963 DCHECK(vd.Is1S() || vd.Is1D());
2964 Emit(FPFormat(vd) | NEON_FRECPX_scalar | Rn(vn) | Rd(vd));
2978 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) {
2981 NEONFP2RegMisc(vd, vn, NEON_FCVTZS);
2983 DCHECK(vd.Is1D() || vd.Is1S() || vd.Is2D() || vd.Is2S() || vd.Is4S());
2984 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm);
2999 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) {
3002 NEONFP2RegMisc(vd, vn, NEON_FCVTZU);
3004 DCHECK(vd.Is1D() || vd.Is1S() || vd.Is2D() || vd.Is2S() || vd.Is4S());
3005 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZU_imm);
3009 void Assembler::NEONFP2RegMisc(const VRegister& vd, const VRegister& vn,
3011 DCHECK(AreSameFormat(vd, vn));
3012 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd));
3015 void Assembler::NEON2RegMisc(const VRegister& vd, const VRegister& vn,
3017 DCHECK(AreSameFormat(vd, vn));
3022 if (vd.IsScalar()) {
3024 format = SFormat(vd);
3026 format = VFormat(vd);
3029 Emit(format | op | Rn(vn) | Rd(vd));
3032 void Assembler::cmeq(const VRegister& vd, const VRegister& vn, int value) {
3033 DCHECK(vd.IsVector() || vd.Is1D());
3034 NEON2RegMisc(vd, vn, NEON_CMEQ_zero, value);
3037 void Assembler::cmge(const VRegister& vd, const VRegister& vn, int value) {
3038 DCHECK(vd.IsVector() || vd.Is1D());
3039 NEON2RegMisc(vd, vn, NEON_CMGE_zero, value);
3042 void Assembler::cmgt(const VRegister& vd, const VRegister& vn, int value) {
3043 DCHECK(vd.IsVector() || vd.Is1D());
3044 NEON2RegMisc(vd, vn, NEON_CMGT_zero, value);
3047 void Assembler::cmle(const VRegister& vd, const VRegister& vn, int value) {
3048 DCHECK(vd.IsVector() || vd.Is1D());
3049 NEON2RegMisc(vd, vn, NEON_CMLE_zero, value);
3052 void Assembler::cmlt(const VRegister& vd, const VRegister& vn, int value) {
3053 DCHECK(vd.IsVector() || vd.Is1D());
3054 NEON2RegMisc(vd, vn, NEON_CMLT_zero, value);
3058 V(add, NEON_ADD, vd.IsVector() || vd.Is1D()) \
3059 V(addp, NEON_ADDP, vd.IsVector() || vd.Is1D()) \
3060 V(sub, NEON_SUB, vd.IsVector() || vd.Is1D()) \
3061 V(cmeq, NEON_CMEQ, vd.IsVector() || vd.Is1D()) \
3062 V(cmge, NEON_CMGE, vd.IsVector() || vd.Is1D()) \
3063 V(cmgt, NEON_CMGT, vd.IsVector() || vd.Is1D()) \
3064 V(cmhi, NEON_CMHI, vd.IsVector() || vd.Is1D()) \
3065 V(cmhs, NEON_CMHS, vd.IsVector() || vd.Is1D()) \
3066 V(cmtst, NEON_CMTST, vd.IsVector() || vd.Is1D()) \
3067 V(sshl, NEON_SSHL, vd.IsVector() || vd.Is1D()) \
3068 V(ushl, NEON_USHL, vd.IsVector() || vd.Is1D()) \
3069 V(srshl, NEON_SRSHL, vd.IsVector() || vd.Is1D()) \
3070 V(urshl, NEON_URSHL, vd.IsVector() || vd.Is1D()) \
3071 V(sqdmulh, NEON_SQDMULH, vd.IsLaneSizeH() || vd.IsLaneSizeS()) \
3072 V(sqrdmulh, NEON_SQRDMULH, vd.IsLaneSizeH() || vd.IsLaneSizeS()) \
3073 V(shadd, NEON_SHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3074 V(uhadd, NEON_UHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3075 V(srhadd, NEON_SRHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3076 V(urhadd, NEON_URHADD, vd.IsVector() && !vd.IsLaneSizeD()) \
3077 V(shsub, NEON_SHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
3078 V(uhsub, NEON_UHSUB, vd.IsVector() && !vd.IsLaneSizeD()) \
3079 V(smax, NEON_SMAX, vd.IsVector() && !vd.IsLaneSizeD()) \
3080 V(smaxp, NEON_SMAXP, vd.IsVector() && !vd.IsLaneSizeD()) \
3081 V(smin, NEON_SMIN, vd.IsVector() && !vd.IsLaneSizeD()) \
3082 V(sminp, NEON_SMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
3083 V(umax, NEON_UMAX, vd.IsVector() && !vd.IsLaneSizeD()) \
3084 V(umaxp, NEON_UMAXP, vd.IsVector() && !vd.IsLaneSizeD()) \
3085 V(umin, NEON_UMIN, vd.IsVector() && !vd.IsLaneSizeD()) \
3086 V(uminp, NEON_UMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
3087 V(saba, NEON_SABA, vd.IsVector() && !vd.IsLaneSizeD()) \
3088 V(sabd, NEON_SABD, vd.IsVector() && !vd.IsLaneSizeD()) \
3089 V(uaba, NEON_UABA, vd.IsVector() && !vd.IsLaneSizeD()) \
3090 V(uabd, NEON_UABD, vd.IsVector() && !vd.IsLaneSizeD()) \
3091 V(mla, NEON_MLA, vd.IsVector() && !vd.IsLaneSizeD()) \
3092 V(mls, NEON_MLS, vd.IsVector() && !vd.IsLaneSizeD()) \
3093 V(mul, NEON_MUL, vd.IsVector() && !vd.IsLaneSizeD()) \
3094 V(and_, NEON_AND, vd.Is8B() || vd.Is16B()) \
3095 V(orr, NEON_ORR, vd.Is8B() || vd.Is16B()) \
3096 V(orn, NEON_ORN, vd.Is8B() || vd.Is16B()) \
3097 V(eor, NEON_EOR, vd.Is8B() || vd.Is16B()) \
3098 V(bic, NEON_BIC, vd.Is8B() || vd.Is16B()) \
3099 V(bit, NEON_BIT, vd.Is8B() || vd.Is16B()) \
3100 V(bif, NEON_BIF, vd.Is8B() || vd.Is16B()) \
3101 V(bsl, NEON_BSL, vd.Is8B() || vd.Is16B()) \
3102 V(pmul, NEON_PMUL, vd.Is8B() || vd.Is16B()) \
3113 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3116 NEON3Same(vd, vn, vm, OP); \
3148 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3151 if ((SCA_OP != 0) && vd.IsScalar()) { \
3152 DCHECK(vd.Is1S() || vd.Is1D()); \
3155 DCHECK(vd.IsVector()); \
3156 DCHECK(vd.Is2S() || vd.Is2D() || vd.Is4S()); \
3159 NEONFP3Same(vd, vn, vm, op); \
3164 void Assembler::addp(const VRegister& vd, const VRegister& vn) {
3165 DCHECK((vd.Is1D() && vn.Is2D()));
3166 Emit(SFormat(vd) | NEON_ADDP_scalar | Rn(vn) | Rd(vd));
3169 void Assembler::faddp(const VRegister& vd, const VRegister& vn) {
3170 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3171 Emit(FPFormat(vd) | NEON_FADDP_scalar | Rn(vn) | Rd(vd));
3174 void Assembler::fmaxp(const VRegister& vd, const VRegister& vn) {
3175 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3176 Emit(FPFormat(vd) | NEON_FMAXP_scalar | Rn(vn) | Rd(vd));
3179 void Assembler::fminp(const VRegister& vd, const VRegister& vn) {
3180 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3181 Emit(FPFormat(vd) | NEON_FMINP_scalar | Rn(vn) | Rd(vd));
3184 void Assembler::fmaxnmp(const VRegister& vd, const VRegister& vn) {
3185 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3186 Emit(FPFormat(vd) | NEON_FMAXNMP_scalar | Rn(vn) | Rd(vd));
3189 void Assembler::fminnmp(const VRegister& vd, const VRegister& vn) {
3190 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3191 Emit(FPFormat(vd) | NEON_FMINNMP_scalar | Rn(vn) | Rd(vd));
3194 void Assembler::orr(const VRegister& vd, const int imm8, const int left_shift) {
3195 NEONModifiedImmShiftLsl(vd, imm8, left_shift, NEONModifiedImmediate_ORR);
3198 void Assembler::mov(const VRegister& vd, const VRegister& vn) {
3199 DCHECK(AreSameFormat(vd, vn));
3200 if (vd.IsD()) {
3201 orr(vd.V8B(), vn.V8B(), vn.V8B());
3203 DCHECK(vd.IsQ());
3204 orr(vd.V16B(), vn.V16B(), vn.V16B());
3208 void Assembler::bic(const VRegister& vd, const int imm8, const int left_shift) {
3209 NEONModifiedImmShiftLsl(vd, imm8, left_shift, NEONModifiedImmediate_BIC);
3212 void Assembler::movi(const VRegister& vd, const uint64_t imm, Shift shift,
3215 if (vd.Is2D() || vd.Is1D()) {
3225 Instr q = vd.Is2D() ? NEON_Q : 0;
3227 ImmNEONabcdefgh(imm8) | NEONCmode(0xE) | Rd(vd));
3230 NEONModifiedImmShiftLsl(vd, static_cast<int>(imm), shift_amount,
3234 NEONModifiedImmShiftMsl(vd, static_cast<int>(imm), shift_amount,
3239 void Assembler::mvn(const VRegister& vd, const VRegister& vn) {
3240 DCHECK(AreSameFormat(vd, vn));
3241 if (vd.IsD()) {
3242 not_(vd.V8B(), vn.V8B());
3244 DCHECK(vd.IsQ());
3245 not_(vd.V16B(), vn.V16B());
3249 void Assembler::mvni(const VRegister& vd, const int imm8, Shift shift,
3253 NEONModifiedImmShiftLsl(vd, imm8, shift_amount, NEONModifiedImmediate_MVNI);
3255 NEONModifiedImmShiftMsl(vd, imm8, shift_amount, NEONModifiedImmediate_MVNI);
3259 void Assembler::NEONFPByElement(const VRegister& vd, const VRegister& vn,
3262 DCHECK(AreSameFormat(vd, vn));
3263 DCHECK((vd.Is2S() && vm.Is1S()) || (vd.Is4S() && vm.Is1S()) ||
3264 (vd.Is1S() && vm.Is1S()) || (vd.Is2D() && vm.Is1D()) ||
3265 (vd.Is1D() && vm.Is1D()));
3270 if (vd.IsScalar()) {
3274 Emit(FPFormat(vd) | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) |
3275 Rn(vn) | Rd(vd));
3278 void Assembler::NEONByElement(const VRegister& vd, const VRegister& vn,
3281 DCHECK(AreSameFormat(vd, vn));
3282 DCHECK((vd.Is4H() && vm.Is1H()) || (vd.Is8H() && vm.Is1H()) ||
3283 (vd.Is1H() && vm.Is1H()) || (vd.Is2S() && vm.Is1S()) ||
3284 (vd.Is4S() && vm.Is1S()) || (vd.Is1S() && vm.Is1S()));
3290 if (vd.IsScalar()) {
3297 Rd(vd));
3300 void Assembler::NEONByElementL(const VRegister& vd, const VRegister& vn,
3303 DCHECK((vd.Is4S() && vn.Is4H() && vm.Is1H()) ||
3304 (vd.Is4S() && vn.Is8H() && vm.Is1H()) ||
3305 (vd.Is1S() && vn.Is1H() && vm.Is1H()) ||
3306 (vd.Is2D() && vn.Is2S() && vm.Is1S()) ||
3307 (vd.Is2D() && vn.Is4S() && vm.Is1S()) ||
3308 (vd.Is1D() && vn.Is1S() && vm.Is1S()));
3315 if (vd.IsScalar()) {
3322 Rd(vd));
3333 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3336 NEONByElement(vd, vn, vm, vm_index, OP); \
3348 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3350 NEONFPByElement(vd, vn, vm, vm_index, OP); \
3376 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3379 NEONByElementL(vd, vn, vm, vm_index, OP); \
3384 void Assembler::suqadd(const VRegister& vd, const VRegister& vn) {
3385 NEON2RegMisc(vd, vn, NEON_SUQADD);
3388 void Assembler::usqadd(const VRegister& vd, const VRegister& vn) {
3389 NEON2RegMisc(vd, vn, NEON_USQADD);
3392 void Assembler::abs(const VRegister& vd, const VRegister& vn) {
3393 DCHECK(vd.IsVector() || vd.Is1D());
3394 NEON2RegMisc(vd, vn, NEON_ABS);
3397 void Assembler::sqabs(const VRegister& vd, const VRegister& vn) {
3398 NEON2RegMisc(vd, vn, NEON_SQABS);
3401 void Assembler::neg(const VRegister& vd, const VRegister& vn) {
3402 DCHECK(vd.IsVector() || vd.Is1D());
3403 NEON2RegMisc(vd, vn, NEON_NEG);
3406 void Assembler::sqneg(const VRegister& vd, const VRegister& vn) {
3407 NEON2RegMisc(vd, vn, NEON_SQNEG);
3410 void Assembler::NEONXtn(const VRegister& vd, const VRegister& vn,
3413 if (vd.IsScalar()) {
3414 DCHECK((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
3415 (vd.Is1S() && vn.Is1D()));
3417 format = SFormat(vd);
3419 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
3420 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
3421 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
3422 format = VFormat(vd);
3424 Emit(format | op | Rn(vn) | Rd(vd));
3427 void Assembler::xtn(const VRegister& vd, const VRegister& vn) {
3428 DCHECK(vd.IsVector() && vd.IsD());
3429 NEONXtn(vd, vn, NEON_XTN);
3432 void Assembler::xtn2(const VRegister& vd, const VRegister& vn) {
3433 DCHECK(vd.IsVector() && vd.IsQ());
3434 NEONXtn(vd, vn, NEON_XTN);
3437 void Assembler::sqxtn(const VRegister& vd, const VRegister& vn) {
3438 DCHECK(vd.IsScalar() || vd.IsD());
3439 NEONXtn(vd, vn, NEON_SQXTN);
3442 void Assembler::sqxtn2(const VRegister& vd, const VRegister& vn) {
3443 DCHECK(vd.IsVector() && vd.IsQ());
3444 NEONXtn(vd, vn, NEON_SQXTN);
3447 void Assembler::sqxtun(const VRegister& vd, const VRegister& vn) {
3448 DCHECK(vd.IsScalar() || vd.IsD());
3449 NEONXtn(vd, vn, NEON_SQXTUN);
3452 void Assembler::sqxtun2(const VRegister& vd, const VRegister& vn) {
3453 DCHECK(vd.IsVector() && vd.IsQ());
3454 NEONXtn(vd, vn, NEON_SQXTUN);
3457 void Assembler::uqxtn(const VRegister& vd, const VRegister& vn) {
3458 DCHECK(vd.IsScalar() || vd.IsD());
3459 NEONXtn(vd, vn, NEON_UQXTN);
3462 void Assembler::uqxtn2(const VRegister& vd, const VRegister& vn) {
3463 DCHECK(vd.IsVector() && vd.IsQ());
3464 NEONXtn(vd, vn, NEON_UQXTN);
3468 void Assembler::not_(const VRegister& vd, const VRegister& vn) {
3469 DCHECK(AreSameFormat(vd, vn));
3470 DCHECK(vd.Is8B() || vd.Is16B());
3471 Emit(VFormat(vd) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
3474 void Assembler::rbit(const VRegister& vd, const VRegister& vn) {
3475 DCHECK(AreSameFormat(vd, vn));
3476 DCHECK(vd.Is8B() || vd.Is16B());
3477 Emit(VFormat(vn) | (1 << NEONSize_offset) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
3480 void Assembler::ext(const VRegister& vd, const VRegister& vn,
3482 DCHECK(AreSameFormat(vd, vn, vm));
3483 DCHECK(vd.Is8B() || vd.Is16B());
3484 DCHECK((0 <= index) && (index < vd.LaneCount()));
3485 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd));
3488 void Assembler::dup(const VRegister& vd, const VRegister& vn, int vn_index) {
3511 if (vd.IsScalar()) {
3515 DCHECK(!vd.Is1D());
3516 q = vd.IsD() ? 0 : NEON_Q;
3520 Rd(vd));
3796 void Assembler::FPDataProcessing1Source(const VRegister& vd,
3799 Emit(FPType(vn) | op | Rn(vn) | Rd(vd));
3820 void Assembler::NEONModifiedImmShiftLsl(const VRegister& vd, const int imm8,
3823 DCHECK(vd.Is8B() || vd.Is16B() || vd.Is4H() || vd.Is8H() || vd.Is2S() ||
3824 vd.Is4S());
3830 if (vd.Is8B() || vd.Is16B()) {
3839 if (vd.Is4H() || vd.Is8H()) {
3846 Instr q = vd.IsQ() ? NEON_Q : 0;
3848 Emit(q | op | ImmNEONabcdefgh(imm8) | NEONCmode(cmode) | Rd(vd));
3851 void Assembler::NEONModifiedImmShiftMsl(const VRegister& vd, const int imm8,
3854 DCHECK(vd.Is2S() || vd.Is4S());
3861 Instr q = vd.IsQ() ? NEON_Q : 0;
3863 Emit(q | op | ImmNEONabcdefgh(imm8) | NEONCmode(cmode) | Rd(vd));