Lines Matching refs:rn
838 void Assembler::add(const Register& rd, const Register& rn,
840 AddSub(rd, rn, operand, LeaveFlags, ADD);
843 void Assembler::adds(const Register& rd, const Register& rn,
845 AddSub(rd, rn, operand, SetFlags, ADD);
848 void Assembler::cmn(const Register& rn, const Operand& operand) {
849 Register zr = AppropriateZeroRegFor(rn);
850 adds(zr, rn, operand);
853 void Assembler::sub(const Register& rd, const Register& rn,
855 AddSub(rd, rn, operand, LeaveFlags, SUB);
858 void Assembler::subs(const Register& rd, const Register& rn,
860 AddSub(rd, rn, operand, SetFlags, SUB);
863 void Assembler::cmp(const Register& rn, const Operand& operand) {
864 Register zr = AppropriateZeroRegFor(rn);
865 subs(zr, rn, operand);
878 void Assembler::adc(const Register& rd, const Register& rn,
880 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
883 void Assembler::adcs(const Register& rd, const Register& rn,
885 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
888 void Assembler::sbc(const Register& rd, const Register& rn,
890 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
893 void Assembler::sbcs(const Register& rd, const Register& rn,
895 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
909 void Assembler::and_(const Register& rd, const Register& rn,
911 Logical(rd, rn, operand, AND);
914 void Assembler::ands(const Register& rd, const Register& rn,
916 Logical(rd, rn, operand, ANDS);
919 void Assembler::tst(const Register& rn, const Operand& operand) {
920 ands(AppropriateZeroRegFor(rn), rn, operand);
923 void Assembler::bic(const Register& rd, const Register& rn,
925 Logical(rd, rn, operand, BIC);
928 void Assembler::bics(const Register& rd, const Register& rn,
930 Logical(rd, rn, operand, BICS);
933 void Assembler::orr(const Register& rd, const Register& rn,
935 Logical(rd, rn, operand, ORR);
938 void Assembler::orn(const Register& rd, const Register& rn,
940 Logical(rd, rn, operand, ORN);
943 void Assembler::eor(const Register& rd, const Register& rn,
945 Logical(rd, rn, operand, EOR);
948 void Assembler::eon(const Register& rd, const Register& rn,
950 Logical(rd, rn, operand, EON);
953 void Assembler::lslv(const Register& rd, const Register& rn,
955 DCHECK(rd.SizeInBits() == rn.SizeInBits());
957 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
960 void Assembler::lsrv(const Register& rd, const Register& rn,
962 DCHECK(rd.SizeInBits() == rn.SizeInBits());
964 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
967 void Assembler::asrv(const Register& rd, const Register& rn,
969 DCHECK(rd.SizeInBits() == rn.SizeInBits());
971 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd));
974 void Assembler::rorv(const Register& rd, const Register& rn,
976 DCHECK(rd.SizeInBits() == rn.SizeInBits());
978 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd));
982 void Assembler::bfm(const Register& rd, const Register& rn, int immr,
984 DCHECK(rd.SizeInBits() == rn.SizeInBits());
987 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd));
990 void Assembler::sbfm(const Register& rd, const Register& rn, int immr,
992 DCHECK(rd.Is64Bits() || rn.Is32Bits());
995 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd));
998 void Assembler::ubfm(const Register& rd, const Register& rn, int immr,
1000 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1003 ImmS(imms, rn.SizeInBits()) | Rn(rn) | Rd(rd));
1006 void Assembler::extr(const Register& rd, const Register& rn, const Register& rm,
1008 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1011 Emit(SF(rd) | EXTR | N | Rm(rm) | ImmS(lsb, rn.SizeInBits()) | Rn(rn) |
1015 void Assembler::csel(const Register& rd, const Register& rn, const Register& rm,
1017 ConditionalSelect(rd, rn, rm, cond, CSEL);
1020 void Assembler::csinc(const Register& rd, const Register& rn,
1022 ConditionalSelect(rd, rn, rm, cond, CSINC);
1025 void Assembler::csinv(const Register& rd, const Register& rn,
1027 ConditionalSelect(rd, rn, rm, cond, CSINV);
1030 void Assembler::csneg(const Register& rd, const Register& rn,
1032 ConditionalSelect(rd, rn, rm, cond, CSNEG);
1047 void Assembler::cinc(const Register& rd, const Register& rn, Condition cond) {
1049 csinc(rd, rn, rn, NegateCondition(cond));
1052 void Assembler::cinv(const Register& rd, const Register& rn, Condition cond) {
1054 csinv(rd, rn, rn, NegateCondition(cond));
1057 void Assembler::cneg(const Register& rd, const Register& rn, Condition cond) {
1059 csneg(rd, rn, rn, NegateCondition(cond));
1062 void Assembler::ConditionalSelect(const Register& rd, const Register& rn,
1065 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1067 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd));
1070 void Assembler::ccmn(const Register& rn, const Operand& operand,
1072 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
1075 void Assembler::ccmp(const Register& rn, const Operand& operand,
1077 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
1080 void Assembler::DataProcessing3Source(const Register& rd, const Register& rn,
1083 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd));
1086 void Assembler::mul(const Register& rd, const Register& rn,
1088 DCHECK(AreSameSizeAndType(rd, rn, rm));
1089 Register zr = AppropriateZeroRegFor(rn);
1090 DataProcessing3Source(rd, rn, rm, zr, MADD);
1093 void Assembler::madd(const Register& rd, const Register& rn, const Register& rm,
1095 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1096 DataProcessing3Source(rd, rn, rm, ra, MADD);
1099 void Assembler::mneg(const Register& rd, const Register& rn,
1101 DCHECK(AreSameSizeAndType(rd, rn, rm));
1102 Register zr = AppropriateZeroRegFor(rn);
1103 DataProcessing3Source(rd, rn, rm, zr, MSUB);
1106 void Assembler::msub(const Register& rd, const Register& rn, const Register& rm,
1108 DCHECK(AreSameSizeAndType(rd, rn, rm, ra));
1109 DataProcessing3Source(rd, rn, rm, ra, MSUB);
1112 void Assembler::smaddl(const Register& rd, const Register& rn,
1115 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1116 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x);
1119 void Assembler::smsubl(const Register& rd, const Register& rn,
1122 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1123 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x);
1126 void Assembler::umaddl(const Register& rd, const Register& rn,
1129 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1130 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x);
1133 void Assembler::umsubl(const Register& rd, const Register& rn,
1136 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1137 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x);
1140 void Assembler::smull(const Register& rd, const Register& rn,
1143 DCHECK(rn.Is32Bits() && rm.Is32Bits());
1144 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x);
1147 void Assembler::smulh(const Register& rd, const Register& rn,
1149 DCHECK(AreSameSizeAndType(rd, rn, rm));
1150 DataProcessing3Source(rd, rn, rm, xzr, SMULH_x);
1153 void Assembler::sdiv(const Register& rd, const Register& rn,
1155 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1157 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd));
1160 void Assembler::udiv(const Register& rd, const Register& rn,
1162 DCHECK(rd.SizeInBits() == rn.SizeInBits());
1164 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd));
1167 void Assembler::rbit(const Register& rd, const Register& rn) {
1168 DataProcessing1Source(rd, rn, RBIT);
1171 void Assembler::rev16(const Register& rd, const Register& rn) {
1172 DataProcessing1Source(rd, rn, REV16);
1175 void Assembler::rev32(const Register& rd, const Register& rn) {
1177 DataProcessing1Source(rd, rn, REV);
1180 void Assembler::rev(const Register& rd, const Register& rn) {
1181 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w);
1184 void Assembler::clz(const Register& rd, const Register& rn) {
1185 DataProcessing1Source(rd, rn, CLZ);
1188 void Assembler::cls(const Register& rd, const Register& rn) {
1189 DataProcessing1Source(rd, rn, CLS);
1353 void Assembler::ldar(const Register& rt, const Register& rn) {
1354 DCHECK(rn.Is64Bits());
1356 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1359 void Assembler::ldaxr(const Register& rt, const Register& rn) {
1360 DCHECK(rn.Is64Bits());
1362 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1365 void Assembler::stlr(const Register& rt, const Register& rn) {
1366 DCHECK(rn.Is64Bits());
1368 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1372 const Register& rn) {
1373 DCHECK(rn.Is64Bits());
1374 DCHECK(rs != rt && rs != rn);
1376 Emit(op | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
1379 void Assembler::ldarb(const Register& rt, const Register& rn) {
1381 DCHECK(rn.Is64Bits());
1382 Emit(LDAR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1385 void Assembler::ldaxrb(const Register& rt, const Register& rn) {
1387 DCHECK(rn.Is64Bits());
1388 Emit(LDAXR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1391 void Assembler::stlrb(const Register& rt, const Register& rn) {
1393 DCHECK(rn.Is64Bits());
1394 Emit(STLR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1398 const Register& rn) {
1401 DCHECK(rn.Is64Bits());
1402 DCHECK(rs != rt && rs != rn);
1403 Emit(STLXR_b | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
1406 void Assembler::ldarh(const Register& rt, const Register& rn) {
1408 DCHECK(rn.Is64Bits());
1409 Emit(LDAR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1412 void Assembler::ldaxrh(const Register& rt, const Register& rn) {
1414 DCHECK(rn.Is64Bits());
1415 Emit(LDAXR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1418 void Assembler::stlrh(const Register& rt, const Register& rn) {
1420 DCHECK(rn.Is64Bits());
1421 Emit(STLR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
1425 const Register& rn) {
1428 DCHECK(rn.Is64Bits());
1429 DCHECK(rs != rt && rs != rn);
1430 Emit(STLXR_h | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
1878 void Assembler::ins(const VRegister& vd, int vd_index, const Register& rn) {
1886 DCHECK(rn.IsW());
1890 DCHECK(rn.IsW());
1894 DCHECK(rn.IsW());
1898 DCHECK(rn.IsX());
1905 Emit(NEON_INS_GENERAL | ImmNEON5(format, vd_index) | Rn(rn) | Rd(vd));
2060 void Assembler::mov(const VRegister& vd, int vd_index, const Register& rn) {
2061 ins(vd, vd_index, rn);
2101 void Assembler::dup(const VRegister& vd, const Register& rn) {
2103 DCHECK_EQ(vd.Is2D(), rn.IsX());
2105 Emit(q | NEON_DUP_GENERAL | ImmNEON5(VFormat(vd), 0) | Rn(rn) | Rd(vd));
2643 void Assembler::fmov(const VRegister& vd, const Register& rn) {
2644 DCHECK_EQ(vd.SizeInBits(), rn.SizeInBits());
2646 Emit(op | Rd(vd) | Rn(rn));
2654 void Assembler::fmov(const VRegister& vd, int index, const Register& rn) {
2655 DCHECK((index == 1) && vd.Is1D() && rn.IsX());
2657 Emit(FMOV_d1_x | Rd(vd) | Rn(rn));
2836 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) {
2839 Emit(SF(rn) | FPType(vd) | SCVTF | Rn(rn) | Rd(vd));
2841 Emit(SF(rn) | FPType(vd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
2846 void Assembler::ucvtf(const VRegister& fd, const Register& rn, int fbits) {
2849 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd));
2851 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) |
3632 void Assembler::AddSub(const Register& rd, const Register& rn,
3634 DCHECK_EQ(rd.SizeInBits(), rn.SizeInBits());
3641 ImmAddSub(static_cast<int>(immediate)) | dest_reg | RnSP(rn));
3653 if (rn.IsSP() || rd.IsSP()) {
3655 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
3658 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
3662 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
3666 void Assembler::AddSubWithCarry(const Register& rd, const Register& rn,
3669 DCHECK_EQ(rd.SizeInBits(), rn.SizeInBits());
3673 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
3729 void Assembler::Logical(const Register& rd, const Register& rn,
3731 DCHECK(rd.SizeInBits() == rn.SizeInBits());
3750 LogicalImmediate(rd, rn, n, imm_s, imm_r, op);
3759 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
3763 void Assembler::LogicalImmediate(const Register& rd, const Register& rn,
3770 Rn(rn));
3773 void Assembler::ConditionalCompare(const Register& rn, const Operand& operand,
3787 Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv));
3790 void Assembler::DataProcessing1Source(const Register& rd, const Register& rn,
3792 DCHECK(rd.SizeInBits() == rn.SizeInBits());
3793 Emit(SF(rn) | op | Rn(rn) | Rd(rd));
3866 void Assembler::EmitShift(const Register& rd, const Register& rn, Shift shift,
3870 lsl(rd, rn, shift_amount);
3873 lsr(rd, rn, shift_amount);
3876 asr(rd, rn, shift_amount);
3879 ror(rd, rn, shift_amount);
3886 void Assembler::EmitExtendShift(const Register& rd, const Register& rn,
3888 DCHECK(rd.SizeInBits() >= rn.SizeInBits());
3891 Register rn_ = Register::Create(rn.code(), rd.SizeInBits());
3911 DCHECK_EQ(rn.SizeInBits(), kXRegSizeInBits);
3925 void Assembler::DataProcShiftedRegister(const Register& rd, const Register& rn,
3929 DCHECK(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount())));
3932 ImmDPShift(operand.shift_amount()) | Rm(operand.reg()) | Rn(rn) |
3936 void Assembler::DataProcExtendedRegister(const Register& rd, const Register& rn,
3943 dest_reg | RnSP(rn));