Lines Matching refs:index
133 int index = base::bits::CountTrailingZeros(list_);
134 DCHECK((1LL << index) & list_);
135 Remove(index);
136 return CPURegister::Create(index, size_, type_);
143 int index = CountLeadingZeros(list_, kRegListSizeInBits);
144 index = kRegListSizeInBits - 1 - index;
145 DCHECK((1LL << index) & list_);
146 Remove(index);
147 return CPURegister::Create(index, size_, type_);
373 EmbeddedObjectIndex index = AddEmbeddedObject(object);
374 set_embedded_object_index_referenced_from(pc, index);
380 EmbeddedObjectIndex index =
382 set_embedded_object_index_referenced_from(pc, index);
1258 // Pre-index and post-index modes.
2244 "Opcodes must match for NEON post index memop.");
2250 // The immediate post index addressing mode is indicated by rm = 31.
2264 // index by immediate of the size of the register list, or post index by a
2556 // Lane size is encoded in the opcode field. Lane index is encoded in the Q,
2654 void Assembler::fmov(const VRegister& vd, int index, const Register& rn) {
2655 DCHECK((index == 1) && vd.Is1D() && rn.IsX());
2656 USE(index);
2660 void Assembler::fmov(const Register& rd, const VRegister& vn, int index) {
2661 DCHECK((index == 1) && vn.Is1D() && rd.IsX());
2662 USE(index);
3481 const VRegister& vm, int index) {
3484 DCHECK((0 <= index) && (index < vd.LaneCount()));
3485 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd));
3987 // Pre-index and post-index modes.
4099 // We find the lowest set bit (as an actual power-of-2 value, not its index)
4176 // Ensure that the index to the multipliers array is within bounds.
4397 EmbeddedObjectIndex index = AddEmbeddedObject(Handle<CodeT>());
4398 RecordRelocInfo(RelocInfo::CODE_TARGET, index, NO_POOL_ENTRY);
4399 DCHECK(is_int32(index));
4400 bl(static_cast<int>(index));