Lines Matching defs:vt4
2364 const VRegister& vt3, const VRegister& vt4,
2368 USE(vt4);
2369 DCHECK(AreSameFormat(vt, vt2, vt3, vt4));
2370 DCHECK(AreConsecutive(vt, vt2, vt3, vt4));
2426 const VRegister& vt3, const VRegister& vt4,
2430 USE(vt4);
2431 DCHECK(AreSameFormat(vt, vt2, vt3, vt4));
2432 DCHECK(AreConsecutive(vt, vt2, vt3, vt4));
2437 const VRegister& vt3, const VRegister& vt4, int lane,
2441 USE(vt4);
2442 DCHECK(AreSameFormat(vt, vt2, vt3, vt4));
2443 DCHECK(AreConsecutive(vt, vt2, vt3, vt4));
2448 const VRegister& vt3, const VRegister& vt4,
2452 USE(vt4);
2453 DCHECK(AreSameFormat(vt, vt2, vt3, vt4));
2454 DCHECK(AreConsecutive(vt, vt2, vt3, vt4));
2480 const VRegister& vt3, const VRegister& vt4,
2484 USE(vt4);
2485 DCHECK(AreSameFormat(vt, vt2, vt3, vt4));
2486 DCHECK(AreConsecutive(vt, vt2, vt3, vt4));
2525 const VRegister& vt3, const VRegister& vt4,
2529 USE(vt4);
2530 DCHECK(AreSameFormat(vt, vt2, vt3, vt4));
2531 DCHECK(AreConsecutive(vt, vt2, vt3, vt4));
2536 const VRegister& vt3, const VRegister& vt4, int lane,
2540 USE(vt4);
2541 DCHECK(AreSameFormat(vt, vt2, vt3, vt4));
2542 DCHECK(AreConsecutive(vt, vt2, vt3, vt4));