Lines Matching defs:src
31 #include "src/codegen/arm64/assembler-arm64.h"
33 #include "src/base/bits.h"
34 #include "src/base/cpu.h"
35 #include "src/base/small-vector.h"
36 #include "src/codegen/arm64/assembler-arm64-inl.h"
37 #include "src/codegen/register-configuration.h"
38 #include "src/codegen/safepoint-table.h"
39 #include "src/codegen/string-constants.h"
40 #include "src/execution/frame-constants.h"
1222 const MemOperand& src) {
1223 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));
1238 const MemOperand& src) {
1240 LoadStorePair(rt, rt2, src, LDPSW_x);
1273 void Assembler::ldrb(const Register& rt, const MemOperand& src) {
1274 LoadStore(rt, src, LDRB_w);
1281 void Assembler::ldrsb(const Register& rt, const MemOperand& src) {
1282 LoadStore(rt, src, rt.Is64Bits() ? LDRSB_x : LDRSB_w);
1285 void Assembler::ldrh(const Register& rt, const MemOperand& src) {
1286 LoadStore(rt, src, LDRH_w);
1293 void Assembler::ldrsh(const Register& rt, const MemOperand& src) {
1294 LoadStore(rt, src, rt.Is64Bits() ? LDRSH_x : LDRSH_w);
1297 void Assembler::ldr(const CPURegister& rt, const MemOperand& src) {
1298 LoadStore(rt, src, LoadOpFor(rt));
1301 void Assembler::str(const CPURegister& rt, const MemOperand& src) {
1302 LoadStore(rt, src, StoreOpFor(rt));
1305 void Assembler::ldrsw(const Register& rt, const MemOperand& src) {
1307 LoadStore(rt, src, LDRSW_x);
2342 void Assembler::ld1(const VRegister& vt, const MemOperand& src) {
2343 LoadStoreStruct(vt, src, NEON_LD1_1v);
2347 const MemOperand& src) {
2351 LoadStoreStruct(vt, src, NEON_LD1_2v);
2355 const VRegister& vt3, const MemOperand& src) {
2360 LoadStoreStruct(vt, src, NEON_LD1_3v);
2365 const MemOperand& src) {
2371 LoadStoreStruct(vt, src, NEON_LD1_4v);
2375 const MemOperand& src) {
2379 LoadStoreStruct(vt, src, NEON_LD2);
2383 const MemOperand& src) {
2387 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad2);
2391 const MemOperand& src) {
2395 LoadStoreStructSingleAllLanes(vt, src, NEON_LD2R);
2399 const VRegister& vt3, const MemOperand& src) {
2404 LoadStoreStruct(vt, src, NEON_LD3);
2408 const VRegister& vt3, int lane, const MemOperand& src) {
2413 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad3);
2417 const VRegister& vt3, const MemOperand& src) {
2422 LoadStoreStructSingleAllLanes(vt, src, NEON_LD3R);
2427 const MemOperand& src) {
2433 LoadStoreStruct(vt, src, NEON_LD4);
2438 const MemOperand& src) {
2444 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad4);
2449 const MemOperand& src) {
2455 LoadStoreStructSingleAllLanes(vt, src, NEON_LD4R);
2458 void Assembler::st1(const VRegister& vt, const MemOperand& src) {
2459 LoadStoreStruct(vt, src, NEON_ST1_1v);
2463 const MemOperand& src) {
2467 LoadStoreStruct(vt, src, NEON_ST1_2v);
2471 const VRegister& vt3, const MemOperand& src) {
2476 LoadStoreStruct(vt, src, NEON_ST1_3v);
2481 const MemOperand& src) {
2487 LoadStoreStruct(vt, src, NEON_ST1_4v);
2588 void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) {
2589 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad1);
2592 void Assembler::ld1r(const VRegister& vt, const MemOperand& src) {
2593 LoadStoreStructSingleAllLanes(vt, src, NEON_LD1R);