Lines Matching defs:shift
1586 int shift, NEONShiftImmediateOp op) {
1588 DCHECK((shift >= 0) && (shift < laneSizeInBits));
1589 NEONShiftImmediate(vd, vn, op, (laneSizeInBits + shift) << 16);
1593 const VRegister& vn, int shift,
1596 DCHECK((shift >= 1) && (shift <= laneSizeInBits));
1597 NEONShiftImmediate(vd, vn, op, ((2 * laneSizeInBits) - shift) << 16);
1601 int shift, NEONShiftImmediateOp op) {
1603 DCHECK((shift >= 0) && (shift < laneSizeInBits));
1604 int immh_immb = (laneSizeInBits + shift) << 16;
1615 int shift, NEONShiftImmediateOp op) {
1618 DCHECK((shift >= 1) && (shift <= laneSizeInBits));
1619 int immh_immb = (2 * laneSizeInBits - shift) << 16;
1636 void Assembler::shl(const VRegister& vd, const VRegister& vn, int shift) {
1638 NEONShiftLeftImmediate(vd, vn, shift, NEON_SHL);
1641 void Assembler::sli(const VRegister& vd, const VRegister& vn, int shift) {
1643 NEONShiftLeftImmediate(vd, vn, shift, NEON_SLI);
1646 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) {
1647 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHL_imm);
1650 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) {
1651 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHLU);
1654 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) {
1655 NEONShiftLeftImmediate(vd, vn, shift, NEON_UQSHL_imm);
1658 void Assembler::sshll(const VRegister& vd, const VRegister& vn, int shift) {
1660 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
1663 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) {
1665 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
1676 void Assembler::ushll(const VRegister& vd, const VRegister& vn, int shift) {
1678 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
1681 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) {
1683 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
1694 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) {
1696 NEONShiftRightImmediate(vd, vn, shift, NEON_SRI);
1699 void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) {
1701 NEONShiftRightImmediate(vd, vn, shift, NEON_SSHR);
1704 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) {
1706 NEONShiftRightImmediate(vd, vn, shift, NEON_USHR);
1709 void Assembler::srshr(const VRegister& vd, const VRegister& vn, int shift) {
1711 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSHR);
1714 void Assembler::urshr(const VRegister& vd, const VRegister& vn, int shift) {
1716 NEONShiftRightImmediate(vd, vn, shift, NEON_URSHR);
1719 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) {
1721 NEONShiftRightImmediate(vd, vn, shift, NEON_SSRA);
1724 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) {
1726 NEONShiftRightImmediate(vd, vn, shift, NEON_USRA);
1729 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) {
1731 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSRA);
1734 void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) {
1736 NEONShiftRightImmediate(vd, vn, shift, NEON_URSRA);
1739 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) {
1741 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
1744 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) {
1746 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
1749 void Assembler::rshrn(const VRegister& vd, const VRegister& vn, int shift) {
1751 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
1754 void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1756 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
1759 void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) {
1761 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
1764 void Assembler::sqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1766 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
1769 void Assembler::sqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
1771 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
1774 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1776 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
1779 void Assembler::sqshrun(const VRegister& vd, const VRegister& vn, int shift) {
1781 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
1784 void Assembler::sqshrun2(const VRegister& vd, const VRegister& vn, int shift) {
1786 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
1789 void Assembler::sqrshrun(const VRegister& vd, const VRegister& vn, int shift) {
1791 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
1794 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) {
1796 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
1799 void Assembler::uqshrn(const VRegister& vd, const VRegister& vn, int shift) {
1801 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
1804 void Assembler::uqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1806 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
1809 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
1811 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
1814 void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1816 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
2907 void Assembler::shll(const VRegister& vd, const VRegister& vn, int shift) {
2908 DCHECK((vd.Is8H() && vn.Is8B() && shift == 8) ||
2909 (vd.Is4S() && vn.Is4H() && shift == 16) ||
2910 (vd.Is2D() && vn.Is2S() && shift == 32));
2911 USE(shift);
2915 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) {
2916 USE(shift);
2917 DCHECK((vd.Is8H() && vn.Is16B() && shift == 8) ||
2918 (vd.Is4S() && vn.Is8H() && shift == 16) ||
2919 (vd.Is2D() && vn.Is4S() && shift == 32));
3212 void Assembler::movi(const VRegister& vd, const uint64_t imm, Shift shift,
3214 DCHECK((shift == LSL) || (shift == MSL));
3228 } else if (shift == LSL) {
3249 void Assembler::mvni(const VRegister& vd, const int imm8, Shift shift,
3251 DCHECK((shift == LSL) || (shift == MSL));
3252 if (shift == LSL) {
3590 void Assembler::MoveWide(const Register& rd, uint64_t imm, int shift,
3601 if (shift >= 0) {
3602 // Explicit shift specified.
3603 DCHECK((shift == 0) || (shift == 16) || (shift == 32) || (shift == 48));
3604 DCHECK(rd.Is64Bits() || (shift == 0) || (shift == 16));
3605 shift /= 16;
3607 // Calculate a new immediate and shift combination to encode the immediate
3609 shift = 0;
3614 shift = 1;
3618 shift = 2;
3622 shift = 3;
3629 ImmMoveWide(static_cast<int>(imm)) | ShiftMoveWide(shift));
3644 DCHECK_NE(operand.shift(), ROR);
3866 void Assembler::EmitShift(const Register& rd, const Register& rn, Shift shift,
3868 switch (shift) {
3894 // Number of bits left in the result that are not introduced by the shift.
3912 // Nothing to extend. Just shift.
3931 Emit(SF(rd) | op | Flags(S) | ShiftDP(operand.shift()) |
3972 Shift shift = addr.shift();
3976 if (shift == LSL) {
3980 // Shifts are encoded in one bit, indicating a left shift by the memory
4088 // shift the value left before duplicating it.