Lines Matching defs:operand
839 const Operand& operand) {
840 AddSub(rd, rn, operand, LeaveFlags, ADD);
844 const Operand& operand) {
845 AddSub(rd, rn, operand, SetFlags, ADD);
848 void Assembler::cmn(const Register& rn, const Operand& operand) {
850 adds(zr, rn, operand);
854 const Operand& operand) {
855 AddSub(rd, rn, operand, LeaveFlags, SUB);
859 const Operand& operand) {
860 AddSub(rd, rn, operand, SetFlags, SUB);
863 void Assembler::cmp(const Register& rn, const Operand& operand) {
865 subs(zr, rn, operand);
868 void Assembler::neg(const Register& rd, const Operand& operand) {
870 sub(rd, zr, operand);
873 void Assembler::negs(const Register& rd, const Operand& operand) {
875 subs(rd, zr, operand);
879 const Operand& operand) {
880 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC);
884 const Operand& operand) {
885 AddSubWithCarry(rd, rn, operand, SetFlags, ADC);
889 const Operand& operand) {
890 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC);
894 const Operand& operand) {
895 AddSubWithCarry(rd, rn, operand, SetFlags, SBC);
898 void Assembler::ngc(const Register& rd, const Operand& operand) {
900 sbc(rd, zr, operand);
903 void Assembler::ngcs(const Register& rd, const Operand& operand) {
905 sbcs(rd, zr, operand);
910 const Operand& operand) {
911 Logical(rd, rn, operand, AND);
915 const Operand& operand) {
916 Logical(rd, rn, operand, ANDS);
919 void Assembler::tst(const Register& rn, const Operand& operand) {
920 ands(AppropriateZeroRegFor(rn), rn, operand);
924 const Operand& operand) {
925 Logical(rd, rn, operand, BIC);
929 const Operand& operand) {
930 Logical(rd, rn, operand, BICS);
934 const Operand& operand) {
935 Logical(rd, rn, operand, ORR);
939 const Operand& operand) {
940 Logical(rd, rn, operand, ORN);
944 const Operand& operand) {
945 Logical(rd, rn, operand, EOR);
949 const Operand& operand) {
950 Logical(rd, rn, operand, EON);
1070 void Assembler::ccmn(const Register& rn, const Operand& operand,
1072 ConditionalCompare(rn, operand, nzcv, cond, CCMN);
1075 void Assembler::ccmp(const Register& rn, const Operand& operand,
1077 ConditionalCompare(rn, operand, nzcv, cond, CCMP);
1335 void Assembler::ldr(const CPURegister& rt, const Operand& operand) {
1336 if (operand.IsHeapObjectRequest()) {
1338 RequestHeapObject(operand.heap_object_request());
1339 ldr(rt, operand.immediate_for_heap_object_request());
1341 ldr(rt, operand.immediate());
1869 // second operand of zero. Otherwise, orr with first operand zr is
2220 void Assembler::mvn(const Register& rd, const Operand& operand) {
2221 orn(rd, AppropriateZeroRegFor(rd), operand);
3633 const Operand& operand, FlagsUpdate S, AddSubOp op) {
3635 DCHECK(!operand.NeedsRelocation(this));
3636 if (operand.IsImmediate()) {
3637 int64_t immediate = operand.ImmediateValue();
3642 } else if (operand.IsShiftedRegister()) {
3643 DCHECK_EQ(operand.reg().SizeInBits(), rd.SizeInBits());
3644 DCHECK_NE(operand.shift(), ROR);
3651 // or their 64-bit register equivalents, convert the operand from shifted to
3655 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
3658 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
3661 DCHECK(operand.IsExtendedRegister());
3662 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
3667 const Operand& operand, FlagsUpdate S,
3670 DCHECK_EQ(rd.SizeInBits(), operand.reg().SizeInBits());
3671 DCHECK(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
3672 DCHECK(!operand.NeedsRelocation(this));
3673 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd));
3730 const Operand& operand, LogicalOp op) {
3732 DCHECK(!operand.NeedsRelocation(this));
3733 if (operand.IsImmediate()) {
3734 int64_t immediate = operand.ImmediateValue();
3756 DCHECK(operand.IsShiftedRegister());
3757 DCHECK(operand.reg().SizeInBits() == rd.SizeInBits());
3759 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
3773 void Assembler::ConditionalCompare(const Register& rn, const Operand& operand,
3777 DCHECK(!operand.NeedsRelocation(this));
3778 if (operand.IsImmediate()) {
3779 int64_t immediate = operand.ImmediateValue();
3784 DCHECK(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
3785 ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
3926 const Operand& operand, FlagsUpdate S,
3928 DCHECK(operand.IsShiftedRegister());
3929 DCHECK(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount())));
3930 DCHECK(!operand.NeedsRelocation(this));
3931 Emit(SF(rd) | op | Flags(S) | ShiftDP(operand.shift()) |
3932 ImmDPShift(operand.shift_amount()) | Rm(operand.reg()) | Rn(rn) |
3937 const Operand& operand, FlagsUpdate S,
3939 DCHECK(!operand.NeedsRelocation(this));
3941 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) |
3942 ExtendMode(operand.extend()) | ImmExtendShift(operand.shift_amount()) |