Lines Matching defs:imm
1345 void Assembler::ldr(const CPURegister& rt, const Immediate& imm) {
1347 RecordRelocInfo(imm.rmode(), imm.value());
2614 void Assembler::fmov(const VRegister& vd, double imm) {
2617 Emit(FMOV_d_imm | Rd(vd) | ImmFP(imm));
2621 Emit(NEON_Q | op | ImmNEONFP(imm) | NEONCmode(0xF) | Rd(vd));
2625 void Assembler::fmov(const VRegister& vd, float imm) {
2628 Emit(FMOV_s_imm | Rd(vd) | ImmFP(imm));
2633 Emit(q | op | ImmNEONFP(imm) | NEONCmode(0xF) | Rd(vd));
3212 void Assembler::movi(const VRegister& vd, const uint64_t imm, Shift shift,
3219 int byte = (imm >> (i * 8)) & 0xFF;
3229 DCHECK(is_uint8(imm));
3230 NEONModifiedImmShiftLsl(vd, static_cast<int>(imm), shift_amount,
3233 DCHECK(is_uint8(imm));
3234 NEONModifiedImmShiftMsl(vd, static_cast<int>(imm), shift_amount,
3569 uint32_t Assembler::FPToImm8(double imm) {
3570 DCHECK(IsImmFP64(imm));
3573 uint64_t bits = bit_cast<uint64_t>(imm);
3584 Instr Assembler::ImmFP(double imm) { return FPToImm8(imm) << ImmFP_offset; }
3585 Instr Assembler::ImmNEONFP(double imm) {
3586 return ImmNEONabcdefgh(FPToImm8(imm));
3590 void Assembler::MoveWide(const Register& rd, uint64_t imm, int shift,
3596 DCHECK(((imm >> kWRegSizeInBits) == 0) ||
3597 ((imm >> (kWRegSizeInBits - 1)) == 0x1FFFFFFFF));
3598 imm &= kWRegMask;
3610 if ((imm & ~0xFFFFULL) == 0) {
3612 } else if ((imm & ~(0xFFFFULL << 16)) == 0) {
3613 imm >>= 16;
3615 } else if ((imm & ~(0xFFFFULL << 32)) == 0) {
3617 imm >>= 32;
3619 } else if ((imm & ~(0xFFFFULL << 48)) == 0) {
3621 imm >>= 48;
3626 DCHECK(is_uint16(imm));
3629 ImmMoveWide(static_cast<int>(imm)) | ShiftMoveWide(shift));
4235 bool Assembler::IsImmFP32(float imm) {
4238 uint32_t bits = bit_cast<uint32_t>(imm);
4258 bool Assembler::IsImmFP64(double imm) {
4262 uint64_t bits = bit_cast<uint64_t>(imm);