Lines Matching defs:vn
1433 void Assembler::NEON3DifferentL(const VRegister& vd, const VRegister& vn,
1435 DCHECK(AreSameFormat(vn, vm));
1436 DCHECK((vn.Is1H() && vd.Is1S()) || (vn.Is1S() && vd.Is1D()) ||
1437 (vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
1438 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
1439 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
1443 format = SFormat(vn);
1445 format = VFormat(vn);
1447 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
1450 void Assembler::NEON3DifferentW(const VRegister& vd, const VRegister& vn,
1452 DCHECK(AreSameFormat(vd, vn));
1456 Emit(VFormat(vm) | vop | Rm(vm) | Rn(vn) | Rd(vd));
1459 void Assembler::NEON3DifferentHN(const VRegister& vd, const VRegister& vn,
1461 DCHECK(AreSameFormat(vm, vn));
1462 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
1463 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
1464 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
1465 Emit(VFormat(vd) | vop | Rm(vm) | Rn(vn) | Rd(vd));
1469 V(pmull, NEON_PMULL, vn.IsVector() && vn.Is8B()) \
1470 V(pmull2, NEON_PMULL2, vn.IsVector() && vn.Is16B()) \
1471 V(saddl, NEON_SADDL, vn.IsVector() && vn.IsD()) \
1472 V(saddl2, NEON_SADDL2, vn.IsVector() && vn.IsQ()) \
1473 V(sabal, NEON_SABAL, vn.IsVector() && vn.IsD()) \
1474 V(sabal2, NEON_SABAL2, vn.IsVector() && vn.IsQ()) \
1475 V(uabal, NEON_UABAL, vn.IsVector() && vn.IsD()) \
1476 V(uabal2, NEON_UABAL2, vn.IsVector() && vn.IsQ()) \
1477 V(sabdl, NEON_SABDL, vn.IsVector() && vn.IsD()) \
1478 V(sabdl2, NEON_SABDL2, vn.IsVector() && vn.IsQ()) \
1479 V(uabdl, NEON_UABDL, vn.IsVector() && vn.IsD()) \
1480 V(uabdl2, NEON_UABDL2, vn.IsVector() && vn.IsQ()) \
1481 V(smlal, NEON_SMLAL, vn.IsVector() && vn.IsD()) \
1482 V(smlal2, NEON_SMLAL2, vn.IsVector() && vn.IsQ()) \
1483 V(umlal, NEON_UMLAL, vn.IsVector() && vn.IsD()) \
1484 V(umlal2, NEON_UMLAL2, vn.IsVector() && vn.IsQ()) \
1485 V(smlsl, NEON_SMLSL, vn.IsVector() && vn.IsD()) \
1486 V(smlsl2, NEON_SMLSL2, vn.IsVector() && vn.IsQ()) \
1487 V(umlsl, NEON_UMLSL, vn.IsVector() && vn.IsD()) \
1488 V(umlsl2, NEON_UMLSL2, vn.IsVector() && vn.IsQ()) \
1489 V(smull, NEON_SMULL, vn.IsVector() && vn.IsD()) \
1490 V(smull2, NEON_SMULL2, vn.IsVector() && vn.IsQ()) \
1491 V(umull, NEON_UMULL, vn.IsVector() && vn.IsD()) \
1492 V(umull2, NEON_UMULL2, vn.IsVector() && vn.IsQ()) \
1493 V(ssubl, NEON_SSUBL, vn.IsVector() && vn.IsD()) \
1494 V(ssubl2, NEON_SSUBL2, vn.IsVector() && vn.IsQ()) \
1495 V(uaddl, NEON_UADDL, vn.IsVector() && vn.IsD()) \
1496 V(uaddl2, NEON_UADDL2, vn.IsVector() && vn.IsQ()) \
1497 V(usubl, NEON_USUBL, vn.IsVector() && vn.IsD()) \
1498 V(usubl2, NEON_USUBL2, vn.IsVector() && vn.IsQ()) \
1499 V(sqdmlal, NEON_SQDMLAL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1500 V(sqdmlal2, NEON_SQDMLAL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
1501 V(sqdmlsl, NEON_SQDMLSL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1502 V(sqdmlsl2, NEON_SQDMLSL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
1503 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
1504 V(sqdmull2, NEON_SQDMULL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S())
1507 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
1510 NEON3DifferentL(vd, vn, vm, OP); \
1526 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
1529 NEON3DifferentHN(vd, vn, vm, OP); \
1534 void Assembler::NEONPerm(const VRegister& vd, const VRegister& vn,
1536 DCHECK(AreSameFormat(vd, vn, vm));
1538 Emit(VFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
1541 void Assembler::trn1(const VRegister& vd, const VRegister& vn,
1543 NEONPerm(vd, vn, vm, NEON_TRN1);
1546 void Assembler::trn2(const VRegister& vd, const VRegister& vn,
1548 NEONPerm(vd, vn, vm, NEON_TRN2);
1551 void Assembler::uzp1(const VRegister& vd, const VRegister& vn,
1553 NEONPerm(vd, vn, vm, NEON_UZP1);
1556 void Assembler::uzp2(const VRegister& vd, const VRegister& vn,
1558 NEONPerm(vd, vn, vm, NEON_UZP2);
1561 void Assembler::zip1(const VRegister& vd, const VRegister& vn,
1563 NEONPerm(vd, vn, vm, NEON_ZIP1);
1566 void Assembler::zip2(const VRegister& vd, const VRegister& vn,
1568 NEONPerm(vd, vn, vm, NEON_ZIP2);
1571 void Assembler::NEONShiftImmediate(const VRegister& vd, const VRegister& vn,
1573 DCHECK(AreSameFormat(vd, vn));
1575 if (vn.IsScalar()) {
1582 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd));
1585 void Assembler::NEONShiftLeftImmediate(const VRegister& vd, const VRegister& vn,
1587 int laneSizeInBits = vn.LaneSizeInBits();
1589 NEONShiftImmediate(vd, vn, op, (laneSizeInBits + shift) << 16);
1593 const VRegister& vn, int shift,
1595 int laneSizeInBits = vn.LaneSizeInBits();
1597 NEONShiftImmediate(vd, vn, op, ((2 * laneSizeInBits) - shift) << 16);
1600 void Assembler::NEONShiftImmediateL(const VRegister& vd, const VRegister& vn,
1602 int laneSizeInBits = vn.LaneSizeInBits();
1606 DCHECK((vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
1607 (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
1608 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
1610 q = vn.IsD() ? 0 : NEON_Q;
1611 Emit(q | op | immh_immb | Rn(vn) | Rd(vd));
1614 void Assembler::NEONShiftImmediateN(const VRegister& vd, const VRegister& vn,
1621 if (vn.IsScalar()) {
1622 DCHECK((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
1623 (vd.Is1S() && vn.Is1D()));
1627 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
1628 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
1629 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
1633 Emit(q | op | scalar | immh_immb | Rn(vn) | Rd(vd));
1636 void Assembler::shl(const VRegister& vd, const VRegister& vn, int shift) {
1638 NEONShiftLeftImmediate(vd, vn, shift, NEON_SHL);
1641 void Assembler::sli(const VRegister& vd, const VRegister& vn, int shift) {
1643 NEONShiftLeftImmediate(vd, vn, shift, NEON_SLI);
1646 void Assembler::sqshl(const VRegister& vd, const VRegister& vn, int shift) {
1647 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHL_imm);
1650 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) {
1651 NEONShiftLeftImmediate(vd, vn, shift, NEON_SQSHLU);
1654 void Assembler::uqshl(const VRegister& vd, const VRegister& vn, int shift) {
1655 NEONShiftLeftImmediate(vd, vn, shift, NEON_UQSHL_imm);
1658 void Assembler::sshll(const VRegister& vd, const VRegister& vn, int shift) {
1659 DCHECK(vn.IsD());
1660 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
1663 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) {
1664 DCHECK(vn.IsQ());
1665 NEONShiftImmediateL(vd, vn, shift, NEON_SSHLL);
1668 void Assembler::sxtl(const VRegister& vd, const VRegister& vn) {
1669 sshll(vd, vn, 0);
1672 void Assembler::sxtl2(const VRegister& vd, const VRegister& vn) {
1673 sshll2(vd, vn, 0);
1676 void Assembler::ushll(const VRegister& vd, const VRegister& vn, int shift) {
1677 DCHECK(vn.IsD());
1678 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
1681 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) {
1682 DCHECK(vn.IsQ());
1683 NEONShiftImmediateL(vd, vn, shift, NEON_USHLL);
1686 void Assembler::uxtl(const VRegister& vd, const VRegister& vn) {
1687 ushll(vd, vn, 0);
1690 void Assembler::uxtl2(const VRegister& vd, const VRegister& vn) {
1691 ushll2(vd, vn, 0);
1694 void Assembler::sri(const VRegister& vd, const VRegister& vn, int shift) {
1696 NEONShiftRightImmediate(vd, vn, shift, NEON_SRI);
1699 void Assembler::sshr(const VRegister& vd, const VRegister& vn, int shift) {
1701 NEONShiftRightImmediate(vd, vn, shift, NEON_SSHR);
1704 void Assembler::ushr(const VRegister& vd, const VRegister& vn, int shift) {
1706 NEONShiftRightImmediate(vd, vn, shift, NEON_USHR);
1709 void Assembler::srshr(const VRegister& vd, const VRegister& vn, int shift) {
1711 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSHR);
1714 void Assembler::urshr(const VRegister& vd, const VRegister& vn, int shift) {
1716 NEONShiftRightImmediate(vd, vn, shift, NEON_URSHR);
1719 void Assembler::ssra(const VRegister& vd, const VRegister& vn, int shift) {
1721 NEONShiftRightImmediate(vd, vn, shift, NEON_SSRA);
1724 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) {
1726 NEONShiftRightImmediate(vd, vn, shift, NEON_USRA);
1729 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) {
1731 NEONShiftRightImmediate(vd, vn, shift, NEON_SRSRA);
1734 void Assembler::ursra(const VRegister& vd, const VRegister& vn, int shift) {
1736 NEONShiftRightImmediate(vd, vn, shift, NEON_URSRA);
1739 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) {
1740 DCHECK(vn.IsVector() && vd.IsD());
1741 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
1744 void Assembler::shrn2(const VRegister& vd, const VRegister& vn, int shift) {
1745 DCHECK(vn.IsVector() && vd.IsQ());
1746 NEONShiftImmediateN(vd, vn, shift, NEON_SHRN);
1749 void Assembler::rshrn(const VRegister& vd, const VRegister& vn, int shift) {
1750 DCHECK(vn.IsVector() && vd.IsD());
1751 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
1754 void Assembler::rshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1755 DCHECK(vn.IsVector() && vd.IsQ());
1756 NEONShiftImmediateN(vd, vn, shift, NEON_RSHRN);
1759 void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) {
1760 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1761 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
1764 void Assembler::sqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1765 DCHECK(vn.IsVector() && vd.IsQ());
1766 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRN);
1769 void Assembler::sqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
1770 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1771 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
1774 void Assembler::sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1775 DCHECK(vn.IsVector() && vd.IsQ());
1776 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRN);
1779 void Assembler::sqshrun(const VRegister& vd, const VRegister& vn, int shift) {
1780 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1781 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
1784 void Assembler::sqshrun2(const VRegister& vd, const VRegister& vn, int shift) {
1785 DCHECK(vn.IsVector() && vd.IsQ());
1786 NEONShiftImmediateN(vd, vn, shift, NEON_SQSHRUN);
1789 void Assembler::sqrshrun(const VRegister& vd, const VRegister& vn, int shift) {
1790 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1791 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
1794 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) {
1795 DCHECK(vn.IsVector() && vd.IsQ());
1796 NEONShiftImmediateN(vd, vn, shift, NEON_SQRSHRUN);
1799 void Assembler::uqshrn(const VRegister& vd, const VRegister& vn, int shift) {
1800 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1801 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
1804 void Assembler::uqshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1805 DCHECK(vn.IsVector() && vd.IsQ());
1806 NEONShiftImmediateN(vd, vn, shift, NEON_UQSHRN);
1809 void Assembler::uqrshrn(const VRegister& vd, const VRegister& vn, int shift) {
1810 DCHECK(vd.IsD() || (vn.IsScalar() && vd.IsScalar()));
1811 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
1814 void Assembler::uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) {
1815 DCHECK(vn.IsVector() && vd.IsQ());
1816 NEONShiftImmediateN(vd, vn, shift, NEON_UQRSHRN);
1819 void Assembler::uaddw(const VRegister& vd, const VRegister& vn,
1822 NEON3DifferentW(vd, vn, vm, NEON_UADDW);
1825 void Assembler::uaddw2(const VRegister& vd, const VRegister& vn,
1828 NEON3DifferentW(vd, vn, vm, NEON_UADDW2);
1831 void Assembler::saddw(const VRegister& vd, const VRegister& vn,
1834 NEON3DifferentW(vd, vn, vm, NEON_SADDW);
1837 void Assembler::saddw2(const VRegister& vd, const VRegister& vn,
1840 NEON3DifferentW(vd, vn, vm, NEON_SADDW2);
1843 void Assembler::usubw(const VRegister& vd, const VRegister& vn,
1846 NEON3DifferentW(vd, vn, vm, NEON_USUBW);
1849 void Assembler::usubw2(const VRegister& vd, const VRegister& vn,
1852 NEON3DifferentW(vd, vn, vm, NEON_USUBW2);
1855 void Assembler::ssubw(const VRegister& vd, const VRegister& vn,
1858 NEON3DifferentW(vd, vn, vm, NEON_SSUBW);
1861 void Assembler::ssubw2(const VRegister& vd, const VRegister& vn,
1864 NEON3DifferentW(vd, vn, vm, NEON_SSUBW2);
1908 void Assembler::mov(const Register& rd, const VRegister& vn, int vn_index) {
1909 DCHECK_GE(vn.SizeInBytes(), 4);
1910 umov(rd, vn, vn_index);
1913 void Assembler::smov(const Register& rd, const VRegister& vn, int vn_index) {
1914 // We support vn arguments of the form vn.VxT() or vn.T(), where x is the
1916 int lane_size = vn.LaneSizeInBytes();
1935 Emit(q | NEON_SMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd));
1938 void Assembler::cls(const VRegister& vd, const VRegister& vn) {
1939 DCHECK(AreSameFormat(vd, vn));
1941 Emit(VFormat(vn) | NEON_CLS | Rn(vn) | Rd(vd));
1944 void Assembler::clz(const VRegister& vd, const VRegister& vn) {
1945 DCHECK(AreSameFormat(vd, vn));
1947 Emit(VFormat(vn) | NEON_CLZ | Rn(vn) | Rd(vd));
1950 void Assembler::cnt(const VRegister& vd, const VRegister& vn) {
1951 DCHECK(AreSameFormat(vd, vn));
1953 Emit(VFormat(vn) | NEON_CNT | Rn(vn) | Rd(vd));
1956 void Assembler::rev16(const VRegister& vd, const VRegister& vn) {
1957 DCHECK(AreSameFormat(vd, vn));
1959 Emit(VFormat(vn) | NEON_REV16 | Rn(vn) | Rd(vd));
1962 void Assembler::rev32(const VRegister& vd, const VRegister& vn) {
1963 DCHECK(AreSameFormat(vd, vn));
1965 Emit(VFormat(vn) | NEON_REV32 | Rn(vn) | Rd(vd));
1968 void Assembler::rev64(const VRegister& vd, const VRegister& vn) {
1969 DCHECK(AreSameFormat(vd, vn));
1971 Emit(VFormat(vn) | NEON_REV64 | Rn(vn) | Rd(vd));
1974 void Assembler::ursqrte(const VRegister& vd, const VRegister& vn) {
1975 DCHECK(AreSameFormat(vd, vn));
1977 Emit(VFormat(vn) | NEON_URSQRTE | Rn(vn) | Rd(vd));
1980 void Assembler::urecpe(const VRegister& vd, const VRegister& vn) {
1981 DCHECK(AreSameFormat(vd, vn));
1983 Emit(VFormat(vn) | NEON_URECPE | Rn(vn) | Rd(vd));
1986 void Assembler::NEONAddlp(const VRegister& vd, const VRegister& vn,
1991 DCHECK((vn.Is8B() && vd.Is4H()) || (vn.Is4H() && vd.Is2S()) ||
1992 (vn.Is2S() && vd.Is1D()) || (vn.Is16B() && vd.Is8H()) ||
1993 (vn.Is8H() && vd.Is4S()) || (vn.Is4S() && vd.Is2D()));
1994 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
1997 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) {
1998 NEONAddlp(vd, vn, NEON_SADDLP);
2001 void Assembler::uaddlp(const VRegister& vd, const VRegister& vn) {
2002 NEONAddlp(vd, vn, NEON_UADDLP);
2005 void Assembler::sadalp(const VRegister& vd, const VRegister& vn) {
2006 NEONAddlp(vd, vn, NEON_SADALP);
2009 void Assembler::uadalp(const VRegister& vd, const VRegister& vn) {
2010 NEONAddlp(vd, vn, NEON_UADALP);
2013 void Assembler::NEONAcrossLanesL(const VRegister& vd, const VRegister& vn,
2015 DCHECK((vn.Is8B() && vd.Is1H()) || (vn.Is16B() && vd.Is1H()) ||
2016 (vn.Is4H() && vd.Is1S()) || (vn.Is8H() && vd.Is1S()) ||
2017 (vn.Is4S() && vd.Is1D()));
2018 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
2021 void Assembler::saddlv(const VRegister& vd, const VRegister& vn) {
2022 NEONAcrossLanesL(vd, vn, NEON_SADDLV);
2025 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) {
2026 NEONAcrossLanesL(vd, vn, NEON_UADDLV);
2029 void Assembler::NEONAcrossLanes(const VRegister& vd, const VRegister& vn,
2031 DCHECK((vn.Is8B() && vd.Is1B()) || (vn.Is16B() && vd.Is1B()) ||
2032 (vn.Is4H() && vd.Is1H()) || (vn.Is8H() && vd.Is1H()) ||
2033 (vn.Is4S() && vd.Is1S()));
2035 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd));
2037 Emit(VFormat(vn) | op | Rn(vn) | Rd(vd));
2053 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
2055 NEONAcrossLanes(vd, vn, OP); \
2064 void Assembler::umov(const Register& rd, const VRegister& vn, int vn_index) {
2065 // We support vn arguments of the form vn.VxT() or vn.T(), where x is the
2067 int lane_size = vn.LaneSizeInBytes();
2093 Emit(q | NEON_UMOV | ImmNEON5(format, vn_index) | Rn(vn) | Rd(rd));
2096 void Assembler::mov(const VRegister& vd, const VRegister& vn, int vn_index) {
2098 dup(vd, vn, vn_index);
2108 void Assembler::ins(const VRegister& vd, int vd_index, const VRegister& vn,
2110 DCHECK(AreSameFormat(vd, vn));
2136 ImmNEON4(format, vn_index) | Rn(vn) | Rd(vd));
2139 void Assembler::NEONTable(const VRegister& vd, const VRegister& vn,
2142 DCHECK(vn.Is16B());
2144 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
2147 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2149 NEONTable(vd, vn, vm, NEON_TBL_1v);
2152 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2155 DCHECK(AreSameFormat(vn, vn2));
2156 DCHECK(AreConsecutive(vn, vn2));
2157 NEONTable(vd, vn, vm, NEON_TBL_2v);
2160 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2165 DCHECK(AreSameFormat(vn, vn2, vn3));
2166 DCHECK(AreConsecutive(vn, vn2, vn3));
2167 NEONTable(vd, vn, vm, NEON_TBL_3v);
2170 void Assembler::tbl(const VRegister& vd, const VRegister& vn,
2176 DCHECK(AreSameFormat(vn, vn2, vn3, vn4));
2177 DCHECK(AreConsecutive(vn, vn2, vn3, vn4));
2178 NEONTable(vd, vn, vm, NEON_TBL_4v);
2181 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2183 NEONTable(vd, vn, vm, NEON_TBX_1v);
2186 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2189 DCHECK(AreSameFormat(vn, vn2));
2190 DCHECK(AreConsecutive(vn, vn2));
2191 NEONTable(vd, vn, vm, NEON_TBX_2v);
2194 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2199 DCHECK(AreSameFormat(vn, vn2, vn3));
2200 DCHECK(AreConsecutive(vn, vn2, vn3));
2201 NEONTable(vd, vn, vm, NEON_TBX_3v);
2204 void Assembler::tbx(const VRegister& vd, const VRegister& vn,
2210 DCHECK(AreSameFormat(vn, vn2, vn3, vn4));
2211 DCHECK(AreConsecutive(vn, vn2, vn3, vn4));
2212 NEONTable(vd, vn, vm, NEON_TBX_4v);
2215 void Assembler::mov(const VRegister& vd, int vd_index, const VRegister& vn,
2217 ins(vd, vd_index, vn, vn_index);
2649 void Assembler::fmov(const VRegister& vd, const VRegister& vn) {
2650 DCHECK_EQ(vd.SizeInBits(), vn.SizeInBits());
2651 Emit(FPType(vd) | FMOV | Rd(vd) | Rn(vn));
2660 void Assembler::fmov(const Register& rd, const VRegister& vn, int index) {
2661 DCHECK((index == 1) && vn.Is1D() && rd.IsX());
2663 Emit(FMOV_x_d1 | Rd(rd) | Rn(vn));
2686 void Assembler::fnmul(const VRegister& vd, const VRegister& vn,
2688 DCHECK(AreSameSizeAndType(vd, vn, vm));
2690 Emit(FPType(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
2720 void Assembler::NEONFPConvertToInt(const Register& rd, const VRegister& vn,
2722 Emit(SF(rd) | FPType(vn) | op | Rn(vn) | Rd(rd));
2725 void Assembler::NEONFPConvertToInt(const VRegister& vd, const VRegister& vn,
2727 if (vn.IsScalar()) {
2728 DCHECK((vd.Is1S() && vn.Is1S()) || (vd.Is1D() && vn.Is1D()));
2731 Emit(FPFormat(vn) | op | Rn(vn) | Rd(vd));
2734 void Assembler::fcvt(const VRegister& vd, const VRegister& vn) {
2737 DCHECK(vn.Is1S() || vn.Is1H());
2738 op = vn.Is1S() ? FCVT_ds : FCVT_dh;
2740 DCHECK(vn.Is1D() || vn.Is1H());
2741 op = vn.Is1D() ? FCVT_sd : FCVT_sh;
2744 DCHECK(vn.Is1D() || vn.Is1S());
2745 op = vn.Is1D() ? FCVT_hd : FCVT_hs;
2747 FPDataProcessing1Source(vd, vn, op);
2750 void Assembler::fcvtl(const VRegister& vd, const VRegister& vn) {
2751 DCHECK((vd.Is4S() && vn.Is4H()) || (vd.Is2D() && vn.Is2S()));
2753 Emit(format | NEON_FCVTL | Rn(vn) | Rd(vd));
2756 void Assembler::fcvtl2(const VRegister& vd, const VRegister& vn) {
2757 DCHECK((vd.Is4S() && vn.Is8H()) || (vd.Is2D() && vn.Is4S()));
2759 Emit(NEON_Q | format | NEON_FCVTL | Rn(vn) | Rd(vd));
2762 void Assembler::fcvtn(const VRegister& vd, const VRegister& vn) {
2763 DCHECK((vn.Is4S() && vd.Is4H()) || (vn.Is2D() && vd.Is2S()));
2764 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0;
2765 Emit(format | NEON_FCVTN | Rn(vn) | Rd(vd));
2768 void Assembler::fcvtn2(const VRegister& vd, const VRegister& vn) {
2769 DCHECK((vn.Is4S() && vd.Is8H()) || (vn.Is2D() && vd.Is4S()));
2770 Instr format = vn.Is2D() ? (1 << NEONSize_offset) : 0;
2771 Emit(NEON_Q | format | NEON_FCVTN | Rn(vn) | Rd(vd));
2774 void Assembler::fcvtxn(const VRegister& vd, const VRegister& vn) {
2777 DCHECK(vd.Is1S() && vn.Is1D());
2778 Emit(format | NEON_FCVTXN_scalar | Rn(vn) | Rd(vd));
2780 DCHECK(vd.Is2S() && vn.Is2D());
2781 Emit(format | NEON_FCVTXN | Rn(vn) | Rd(vd));
2785 void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) {
2786 DCHECK(vd.Is4S() && vn.Is2D());
2788 Emit(NEON_Q | format | NEON_FCVTXN | Rn(vn) | Rd(vd));
2791 void Assembler::fjcvtzs(const Register& rd, const VRegister& vn) {
2792 DCHECK(rd.IsW() && vn.Is1D());
2793 Emit(FJCVTZS | Rn(vn) | Rd(rd));
2807 void Assembler::FN(const Register& rd, const VRegister& vn) { \
2808 NEONFPConvertToInt(rd, vn, SCA_OP); \
2810 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
2811 NEONFPConvertToInt(vd, vn, VEC_OP); \
2816 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) {
2819 NEONFP2RegMisc(vd, vn, NEON_SCVTF);
2822 NEONShiftRightImmediate(vd, vn, fbits, NEON_SCVTF_imm);
2826 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) {
2829 NEONFP2RegMisc(vd, vn, NEON_UCVTF);
2832 NEONShiftRightImmediate(vd, vn, fbits, NEON_UCVTF_imm);
2856 void Assembler::NEON3Same(const VRegister& vd, const VRegister& vn,
2858 DCHECK(AreSameFormat(vd, vn, vm));
2869 Emit(format | op | Rm(vm) | Rn(vn) | Rd(vd));
2872 void Assembler::NEONFP3Same(const VRegister& vd, const VRegister& vn,
2874 DCHECK(AreSameFormat(vd, vn, vm));
2875 Emit(FPFormat(vd) | op | Rm(vm) | Rn(vn) | Rd(vd));
2893 void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
2902 NEONFP2RegMisc(vd, vn, op); \
2907 void Assembler::shll(const VRegister& vd, const VRegister& vn, int shift) {
2908 DCHECK((vd.Is8H() && vn.Is8B() && shift == 8) ||
2909 (vd.Is4S() && vn.Is4H() && shift == 16) ||
2910 (vd.Is2D() && vn.Is2S() && shift == 32));
2912 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd));
2915 void Assembler::shll2(const VRegister& vd, const VRegister& vn, int shift) {
2917 DCHECK((vd.Is8H() && vn.Is16B() && shift == 8) ||
2918 (vd.Is4S() && vn.Is8H() && shift == 16) ||
2919 (vd.Is2D() && vn.Is4S() && shift == 32));
2920 Emit(VFormat(vn) | NEON_SHLL | Rn(vn) | Rd(vd));
2923 void Assembler::NEONFP2RegMisc(const VRegister& vd, const VRegister& vn,
2925 DCHECK(AreSameFormat(vd, vn));
2937 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd));
2940 void Assembler::fcmeq(const VRegister& vd, const VRegister& vn, double value) {
2941 NEONFP2RegMisc(vd, vn, NEON_FCMEQ_zero, value);
2944 void Assembler::fcmge(const VRegister& vd, const VRegister& vn, double value) {
2945 NEONFP2RegMisc(vd, vn, NEON_FCMGE_zero, value);
2948 void Assembler::fcmgt(const VRegister& vd, const VRegister& vn, double value) {
2949 NEONFP2RegMisc(vd, vn, NEON_FCMGT_zero, value);
2952 void Assembler::fcmle(const VRegister& vd, const VRegister& vn, double value) {
2953 NEONFP2RegMisc(vd, vn, NEON_FCMLE_zero, value);
2956 void Assembler::fcmlt(const VRegister& vd, const VRegister& vn, double value) {
2957 NEONFP2RegMisc(vd, vn, NEON_FCMLT_zero, value);
2960 void Assembler::frecpx(const VRegister& vd, const VRegister& vn) {
2962 DCHECK(AreSameFormat(vd, vn));
2964 Emit(FPFormat(vd) | NEON_FRECPX_scalar | Rn(vn) | Rd(vd));
2967 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) {
2968 DCHECK(vn.Is1S() || vn.Is1D());
2971 Emit(SF(rd) | FPType(vn) | FCVTZS | Rn(vn) | Rd(rd));
2973 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) |
2978 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) {
2981 NEONFP2RegMisc(vd, vn, NEON_FCVTZS);
2984 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm);
2988 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) {
2989 DCHECK(vn.Is1S() || vn.Is1D());
2992 Emit(SF(rd) | FPType(vn) | FCVTZU | Rn(vn) | Rd(rd));
2994 Emit(SF(rd) | FPType(vn) | FCVTZU_fixed | FPScale(64 - fbits) | Rn(vn) |
2999 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) {
3002 NEONFP2RegMisc(vd, vn, NEON_FCVTZU);
3005 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZU_imm);
3009 void Assembler::NEONFP2RegMisc(const VRegister& vd, const VRegister& vn,
3011 DCHECK(AreSameFormat(vd, vn));
3012 Emit(FPFormat(vd) | op | Rn(vn) | Rd(vd));
3015 void Assembler::NEON2RegMisc(const VRegister& vd, const VRegister& vn,
3017 DCHECK(AreSameFormat(vd, vn));
3029 Emit(format | op | Rn(vn) | Rd(vd));
3032 void Assembler::cmeq(const VRegister& vd, const VRegister& vn, int value) {
3034 NEON2RegMisc(vd, vn, NEON_CMEQ_zero, value);
3037 void Assembler::cmge(const VRegister& vd, const VRegister& vn, int value) {
3039 NEON2RegMisc(vd, vn, NEON_CMGE_zero, value);
3042 void Assembler::cmgt(const VRegister& vd, const VRegister& vn, int value) {
3044 NEON2RegMisc(vd, vn, NEON_CMGT_zero, value);
3047 void Assembler::cmle(const VRegister& vd, const VRegister& vn, int value) {
3049 NEON2RegMisc(vd, vn, NEON_CMLE_zero, value);
3052 void Assembler::cmlt(const VRegister& vd, const VRegister& vn, int value) {
3054 NEON2RegMisc(vd, vn, NEON_CMLT_zero, value);
3113 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3116 NEON3Same(vd, vn, vm, OP); \
3148 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3159 NEONFP3Same(vd, vn, vm, op); \
3164 void Assembler::addp(const VRegister& vd, const VRegister& vn) {
3165 DCHECK((vd.Is1D() && vn.Is2D()));
3166 Emit(SFormat(vd) | NEON_ADDP_scalar | Rn(vn) | Rd(vd));
3169 void Assembler::faddp(const VRegister& vd, const VRegister& vn) {
3170 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3171 Emit(FPFormat(vd) | NEON_FADDP_scalar | Rn(vn) | Rd(vd));
3174 void Assembler::fmaxp(const VRegister& vd, const VRegister& vn) {
3175 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3176 Emit(FPFormat(vd) | NEON_FMAXP_scalar | Rn(vn) | Rd(vd));
3179 void Assembler::fminp(const VRegister& vd, const VRegister& vn) {
3180 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3181 Emit(FPFormat(vd) | NEON_FMINP_scalar | Rn(vn) | Rd(vd));
3184 void Assembler::fmaxnmp(const VRegister& vd, const VRegister& vn) {
3185 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3186 Emit(FPFormat(vd) | NEON_FMAXNMP_scalar | Rn(vn) | Rd(vd));
3189 void Assembler::fminnmp(const VRegister& vd, const VRegister& vn) {
3190 DCHECK((vd.Is1S() && vn.Is2S()) || (vd.Is1D() && vn.Is2D()));
3191 Emit(FPFormat(vd) | NEON_FMINNMP_scalar | Rn(vn) | Rd(vd));
3198 void Assembler::mov(const VRegister& vd, const VRegister& vn) {
3199 DCHECK(AreSameFormat(vd, vn));
3201 orr(vd.V8B(), vn.V8B(), vn.V8B());
3204 orr(vd.V16B(), vn.V16B(), vn.V16B());
3239 void Assembler::mvn(const VRegister& vd, const VRegister& vn) {
3240 DCHECK(AreSameFormat(vd, vn));
3242 not_(vd.V8B(), vn.V8B());
3245 not_(vd.V16B(), vn.V16B());
3259 void Assembler::NEONFPByElement(const VRegister& vd, const VRegister& vn,
3262 DCHECK(AreSameFormat(vd, vn));
3275 Rn(vn) | Rd(vd));
3278 void Assembler::NEONByElement(const VRegister& vd, const VRegister& vn,
3281 DCHECK(AreSameFormat(vd, vn));
3292 format = SFormat(vn);
3294 format = VFormat(vn);
3296 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
3300 void Assembler::NEONByElementL(const VRegister& vd, const VRegister& vn,
3303 DCHECK((vd.Is4S() && vn.Is4H() && vm.Is1H()) ||
3304 (vd.Is4S() && vn.Is8H() && vm.Is1H()) ||
3305 (vd.Is1S() && vn.Is1H() && vm.Is1H()) ||
3306 (vd.Is2D() && vn.Is2S() && vm.Is1S()) ||
3307 (vd.Is2D() && vn.Is4S() && vm.Is1S()) ||
3308 (vd.Is1D() && vn.Is1S() && vm.Is1S()));
3317 format = SFormat(vn);
3319 format = VFormat(vn);
3321 Emit(format | op | ImmNEONHLM(vm_index, index_num_bits) | Rm(vm) | Rn(vn) |
3326 V(mul, NEON_MUL_byelement, vn.IsVector()) \
3327 V(mla, NEON_MLA_byelement, vn.IsVector()) \
3328 V(mls, NEON_MLS_byelement, vn.IsVector()) \
3333 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3336 NEONByElement(vd, vn, vm, vm_index, OP); \
3348 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3350 NEONFPByElement(vd, vn, vm, vm_index, OP); \
3356 V(sqdmull, NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD()) \
3357 V(sqdmull2, NEON_SQDMULL_byelement, vn.IsVector() && vn.IsQ()) \
3358 V(sqdmlal, NEON_SQDMLAL_byelement, vn.IsScalar() || vn.IsD()) \
3359 V(sqdmlal2, NEON_SQDMLAL_byelement, vn.IsVector() && vn.IsQ()) \
3360 V(sqdmlsl, NEON_SQDMLSL_byelement, vn.IsScalar() || vn.IsD()) \
3361 V(sqdmlsl2, NEON_SQDMLSL_byelement, vn.IsVector() && vn.IsQ()) \
3362 V(smull, NEON_SMULL_byelement, vn.IsVector() && vn.IsD()) \
3363 V(smull2, NEON_SMULL_byelement, vn.IsVector() && vn.IsQ()) \
3364 V(umull, NEON_UMULL_byelement, vn.IsVector() && vn.IsD()) \
3365 V(umull2, NEON_UMULL_byelement, vn.IsVector() && vn.IsQ()) \
3366 V(smlal, NEON_SMLAL_byelement, vn.IsVector() && vn.IsD()) \
3367 V(smlal2, NEON_SMLAL_byelement, vn.IsVector() && vn.IsQ()) \
3368 V(umlal, NEON_UMLAL_byelement, vn.IsVector() && vn.IsD()) \
3369 V(umlal2, NEON_UMLAL_byelement, vn.IsVector() && vn.IsQ()) \
3370 V(smlsl, NEON_SMLSL_byelement, vn.IsVector() && vn.IsD()) \
3371 V(smlsl2, NEON_SMLSL_byelement, vn.IsVector() && vn.IsQ()) \
3372 V(umlsl, NEON_UMLSL_byelement, vn.IsVector() && vn.IsD()) \
3373 V(umlsl2, NEON_UMLSL_byelement, vn.IsVector() && vn.IsQ())
3376 void Assembler::FN(const VRegister& vd, const VRegister& vn, \
3379 NEONByElementL(vd, vn, vm, vm_index, OP); \
3384 void Assembler::suqadd(const VRegister& vd, const VRegister& vn) {
3385 NEON2RegMisc(vd, vn, NEON_SUQADD);
3388 void Assembler::usqadd(const VRegister& vd, const VRegister& vn) {
3389 NEON2RegMisc(vd, vn, NEON_USQADD);
3392 void Assembler::abs(const VRegister& vd, const VRegister& vn) {
3394 NEON2RegMisc(vd, vn, NEON_ABS);
3397 void Assembler::sqabs(const VRegister& vd, const VRegister& vn) {
3398 NEON2RegMisc(vd, vn, NEON_SQABS);
3401 void Assembler::neg(const VRegister& vd, const VRegister& vn) {
3403 NEON2RegMisc(vd, vn, NEON_NEG);
3406 void Assembler::sqneg(const VRegister& vd, const VRegister& vn) {
3407 NEON2RegMisc(vd, vn, NEON_SQNEG);
3410 void Assembler::NEONXtn(const VRegister& vd, const VRegister& vn,
3414 DCHECK((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
3415 (vd.Is1S() && vn.Is1D()));
3419 DCHECK((vd.Is8B() && vn.Is8H()) || (vd.Is4H() && vn.Is4S()) ||
3420 (vd.Is2S() && vn.Is2D()) || (vd.Is16B() && vn.Is8H()) ||
3421 (vd.Is8H() && vn.Is4S()) || (vd.Is4S() && vn.Is2D()));
3424 Emit(format | op | Rn(vn) | Rd(vd));
3427 void Assembler::xtn(const VRegister& vd, const VRegister& vn) {
3429 NEONXtn(vd, vn, NEON_XTN);
3432 void Assembler::xtn2(const VRegister& vd, const VRegister& vn) {
3434 NEONXtn(vd, vn, NEON_XTN);
3437 void Assembler::sqxtn(const VRegister& vd, const VRegister& vn) {
3439 NEONXtn(vd, vn, NEON_SQXTN);
3442 void Assembler::sqxtn2(const VRegister& vd, const VRegister& vn) {
3444 NEONXtn(vd, vn, NEON_SQXTN);
3447 void Assembler::sqxtun(const VRegister& vd, const VRegister& vn) {
3449 NEONXtn(vd, vn, NEON_SQXTUN);
3452 void Assembler::sqxtun2(const VRegister& vd, const VRegister& vn) {
3454 NEONXtn(vd, vn, NEON_SQXTUN);
3457 void Assembler::uqxtn(const VRegister& vd, const VRegister& vn) {
3459 NEONXtn(vd, vn, NEON_UQXTN);
3462 void Assembler::uqxtn2(const VRegister& vd, const VRegister& vn) {
3464 NEONXtn(vd, vn, NEON_UQXTN);
3468 void Assembler::not_(const VRegister& vd, const VRegister& vn) {
3469 DCHECK(AreSameFormat(vd, vn));
3471 Emit(VFormat(vd) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
3474 void Assembler::rbit(const VRegister& vd, const VRegister& vn) {
3475 DCHECK(AreSameFormat(vd, vn));
3477 Emit(VFormat(vn) | (1 << NEONSize_offset) | NEON_RBIT_NOT | Rn(vn) | Rd(vd));
3480 void Assembler::ext(const VRegister& vd, const VRegister& vn,
3482 DCHECK(AreSameFormat(vd, vn, vm));
3485 Emit(VFormat(vd) | NEON_EXT | Rm(vm) | ImmNEONExt(index) | Rn(vn) | Rd(vd));
3488 void Assembler::dup(const VRegister& vd, const VRegister& vn, int vn_index) {
3491 // We support vn arguments of the form vn.VxT() or vn.T(), where x is the
3493 int lane_size = vn.LaneSizeInBytes();
3519 Emit(q | scalar | NEON_DUP_ELEMENT | ImmNEON5(format, vn_index) | Rn(vn) |
3797 const VRegister& vn,
3799 Emit(FPType(vn) | op | Rn(vn) | Rd(vd));