Lines Matching defs:reg
245 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
247 reg_(reg),
251 DCHECK(reg.Is64Bits() || (shift_amount < kWRegSizeInBits));
252 DCHECK(reg.Is32Bits() || (shift_amount < kXRegSizeInBits));
253 DCHECK_IMPLIES(reg.IsSP(), shift_amount == 0);
256 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
258 reg_(reg),
262 DCHECK(reg.is_valid());
264 DCHECK(!reg.IsSP());
267 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
299 return reg().IsZero();
344 Register Operand::reg() const {
424 regoffset_ = offset.reg();
438 regoffset_ = offset.reg();
1064 const Register& Assembler::AppropriateZeroRegFor(const CPURegister& reg) const {
1065 return reg.Is64Bits() ? xzr : wzr;