Lines Matching refs:src3
108 void Push(Register src1, Register src2, Register src3, Condition cond = al) {
110 if (src2.code() > src3.code()) {
111 stm(db_w, sp, {src1, src2, src3}, cond);
114 str(src3, MemOperand(sp, 4, NegPreIndex), cond);
118 Push(src2, src3, cond);
123 void Push(Register src1, Register src2, Register src3, Register src4,
126 if (src2.code() > src3.code()) {
127 if (src3.code() > src4.code()) {
128 stm(db_w, sp, {src1, src2, src3, src4}, cond);
130 stm(db_w, sp, {src1, src2, src3}, cond);
135 Push(src3, src4, cond);
139 Push(src2, src3, src4, cond);
144 void Push(Register src1, Register src2, Register src3, Register src4,
147 if (src2.code() > src3.code()) {
148 if (src3.code() > src4.code()) {
150 stm(db_w, sp, {src1, src2, src3, src4, src5}, cond);
152 stm(db_w, sp, {src1, src2, src3, src4}, cond);
156 stm(db_w, sp, {src1, src2, src3}, cond);
161 Push(src3, src4, src5, cond);
165 Push(src2, src3, src4, src5, cond);
189 void Pop(Register src1, Register src2, Register src3, Condition cond = al) {
190 DCHECK(!AreAliased(src1, src2, src3));
192 if (src2.code() > src3.code()) {
193 ldm(ia_w, sp, {src1, src2, src3}, cond);
195 ldr(src3, MemOperand(sp, 4, PostIndex), cond);
199 Pop(src2, src3, cond);
205 void Pop(Register src1, Register src2, Register src3, Register src4,
207 DCHECK(!AreAliased(src1, src2, src3, src4));
209 if (src2.code() > src3.code()) {
210 if (src3.code() > src4.code()) {
211 ldm(ia_w, sp, {src1, src2, src3, src4}, cond);
214 ldm(ia_w, sp, {src1, src2, src3}, cond);
217 Pop(src3, src4, cond);
221 Pop(src2, src3, src4, cond);