Lines Matching refs:src
37 #include "src/codegen/arm/assembler-arm.h"
41 #include "src/base/bits.h"
42 #include "src/base/cpu.h"
43 #include "src/base/overflowing-math.h"
44 #include "src/codegen/arm/assembler-arm-inl.h"
45 #include "src/codegen/assembler-inl.h"
46 #include "src/codegen/machine-type.h"
47 #include "src/codegen/macro-assembler.h"
48 #include "src/codegen/string-constants.h"
49 #include "src/deoptimizer/deoptimizer.h"
50 #include "src/objects/objects-inl.h"
1616 void Assembler::cmp_raw_immediate(Register src, int raw_immediate,
1619 emit(cond | I | CMP | S | src.code() << 16 | raw_immediate);
1636 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
1639 DCHECK(!(src.IsRegister() && src.rm() == dst && s == LeaveCC && cond == al));
1640 AddrMode1(cond | MOV | s, dst, no_reg, src);
1643 void Assembler::mov(Register dst, Register src, SBit s, Condition cond) {
1644 mov(dst, Operand(src), s, cond);
1700 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
1701 AddrMode1(cond | MVN | s, dst, no_reg, src);
1817 void Assembler::clz(Register dst, Register src, Condition cond) {
1818 DCHECK(dst != pc && src != pc);
1820 src.code());
1826 void Assembler::usat(Register dst, int satpos, const Operand& src,
1828 DCHECK(dst != pc && src.rm_ != pc);
1830 DCHECK(src.IsImmediateShiftedRegister());
1831 DCHECK((src.shift_op_ == ASR) || (src.shift_op_ == LSL));
1834 if (src.shift_op_ == ASR) {
1839 src.shift_imm_ * B7 | sh * B6 | 0x1 * B4 | src.rm_.code());
1847 // ubfx dst, src, #lsb, #width
1848 void Assembler::ubfx(Register dst, Register src, int lsb, int width,
1851 DCHECK(dst != pc && src != pc);
1855 lsb * B7 | B6 | B4 | src.code());
1862 // sbfx dst, src, #lsb, #width
1863 void Assembler::sbfx(Register dst, Register src, int lsb, int width,
1866 DCHECK(dst != pc && src != pc);
1870 lsb * B7 | B6 | B4 | src.code());
1889 // bfi dst, src, #lsb, #width
1890 void Assembler::bfi(Register dst, Register src, int lsb, int width,
1893 DCHECK(dst != pc && src != pc);
1898 src.code());
1932 void Assembler::sxtb(Register dst, Register src, int rotate, Condition cond) {
1937 DCHECK(src != pc);
1940 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
1956 void Assembler::sxth(Register dst, Register src, int rotate, Condition cond) {
1961 DCHECK(src != pc);
1964 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
1980 void Assembler::uxtb(Register dst, Register src, int rotate, Condition cond) {
1985 DCHECK(src != pc);
1988 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
2004 void Assembler::uxtb16(Register dst, Register src, int rotate, Condition cond) {
2009 DCHECK(src != pc);
2012 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
2015 void Assembler::uxth(Register dst, Register src, int rotate, Condition cond) {
2020 DCHECK(src != pc);
2023 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
2039 void Assembler::rbit(Register dst, Register src, Condition cond) {
2044 DCHECK(src != pc);
2045 emit(cond | 0x6FF * B16 | dst.code() * B12 | 0xF3 * B4 | src.code());
2048 void Assembler::rev(Register dst, Register src, Condition cond) {
2052 DCHECK(src != pc);
2053 emit(cond | 0x6BF * B16 | dst.code() * B12 | 0xF3 * B4 | src.code());
2062 void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
2067 if (src.IsImmediate()) {
2071 if (src.MustOutputRelocInfo(this) ||
2072 !FitsShifter(src.immediate(), &rotate_imm, &immed_8, nullptr)) {
2077 Move32BitImmediate(scratch, src);
2083 DCHECK(src.IsRegister()); // Only rm is allowed.
2084 instr = src.rm_.code();
2090 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
2091 AddrMode2(cond | B26 | L, dst, src);
2094 void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
2095 AddrMode2(cond | B26, src, dst);
2098 void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
2099 AddrMode2(cond | B26 | B | L, dst, src);
2102 void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
2103 AddrMode2(cond | B26 | B, src, dst);
2106 void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
2107 AddrMode3(cond | L | B7 | H | B4, dst, src);
2110 void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
2111 AddrMode3(cond | B7 | H | B4, src, dst);
2114 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
2115 AddrMode3(cond | L | B7 | S6 | B4, dst, src);
2118 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
2119 AddrMode3(cond | L | B7 | S6 | H | B4, dst, src);
2122 void Assembler::ldrd(Register dst1, Register dst2, const MemOperand& src,
2124 DCHECK(src.rm() == no_reg);
2128 AddrMode3(cond | B7 | B6 | B4, dst1, src);
2151 void Assembler::ldrex(Register dst, Register src, Condition cond) {
2155 DCHECK(src != pc);
2156 emit(cond | B24 | B23 | B20 | src.code() * B16 | dst.code() * B12 | 0xF9F);
2173 void Assembler::ldrexb(Register dst, Register src, Condition cond) {
2177 DCHECK(src != pc);
2178 emit(cond | B24 | B23 | B22 | B20 | src.code() * B16 | dst.code() * B12 |
2196 void Assembler::ldrexh(Register dst, Register src, Condition cond) {
2200 DCHECK(src != pc);
2201 emit(cond | B24 | B23 | B22 | B21 | B20 | src.code() * B16 |
2219 void Assembler::ldrexd(Register dst1, Register dst2, Register src,
2227 emit(cond | B24 | B23 | B21 | B20 | src.code() * B16 | dst1.code() * B12 |
2280 void Assembler::stm(BlockAddrMode am, Register base, RegList src,
2282 AddrMode4(cond | B27 | am, base, src);
2400 void Assembler::ldc(Coprocessor coproc, CRegister crd, const MemOperand& src,
2402 AddrMode5(cond | B27 | B26 | l | L | coproc * B8, crd, src);
2413 void Assembler::ldc2(Coprocessor coproc, CRegister crd, const MemOperand& src,
2415 ldc(coproc, crd, src, l, kSpecialCondition);
2524 void Assembler::vstr(const DwVfpRegister src, const Register base, int offset,
2530 DCHECK(VfpRegisterIsAvailable(src));
2539 src.split_code(&vd, &d);
2560 void Assembler::vstr(const DwVfpRegister src, const MemOperand& operand,
2562 DCHECK(VfpRegisterIsAvailable(src));
2569 vstr(src, scratch, 0, cond);
2571 vstr(src, operand.rn(), operand.offset(), cond);
2575 void Assembler::vstr(const SwVfpRegister src, const Register base, int offset,
2588 src.split_code(&sd, &d);
2609 void Assembler::vstr(const SwVfpRegister src, const MemOperand& operand,
2617 vstr(src, scratch, 0, cond);
2619 vstr(src, operand.rn(), operand.offset(), cond);
2881 void Assembler::vmov(const SwVfpRegister dst, const SwVfpRegister src,
2887 src.split_code(&sm, &m);
2892 void Assembler::vmov(const DwVfpRegister dst, const DwVfpRegister src,
2899 DCHECK(VfpRegisterIsAvailable(src));
2903 src.split_code(&vm, &m);
2923 const DwVfpRegister src, const Condition cond) {
2928 DCHECK(VfpRegisterIsAvailable(src));
2931 src.split_code(&vm, &m);
2936 void Assembler::vmov(const SwVfpRegister dst, const Register src,
2942 DCHECK(src != pc);
2945 emit(cond | 0xE * B24 | sn * B16 | src.code() * B12 | 0xA * B8 | n * B7 | B4);
2948 void Assembler::vmov(const Register dst, const SwVfpRegister src,
2956 src.split_code(&sn, &n);
3055 void Assembler::vcvt_f64_s32(const DwVfpRegister dst, const SwVfpRegister src,
3058 emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond));
3061 void Assembler::vcvt_f32_s32(const SwVfpRegister dst, const SwVfpRegister src,
3063 emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond));
3066 void Assembler::vcvt_f64_u32(const DwVfpRegister dst, const SwVfpRegister src,
3069 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond));
3072 void Assembler::vcvt_f32_u32(const SwVfpRegister dst, const SwVfpRegister src,
3074 emit(EncodeVCVT(F32, dst.code(), U32, src.code(), mode, cond));
3077 void Assembler::vcvt_s32_f32(const SwVfpRegister dst, const SwVfpRegister src,
3079 emit(EncodeVCVT(S32, dst.code(), F32, src.code(), mode, cond));
3082 void Assembler::vcvt_u32_f32(const SwVfpRegister dst, const SwVfpRegister src,
3084 emit(EncodeVCVT(U32, dst.code(), F32, src.code(), mode, cond));
3087 void Assembler::vcvt_s32_f64(const SwVfpRegister dst, const DwVfpRegister src,
3089 DCHECK(VfpRegisterIsAvailable(src));
3090 emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond));
3093 void Assembler::vcvt_u32_f64(const SwVfpRegister dst, const DwVfpRegister src,
3095 DCHECK(VfpRegisterIsAvailable(src));
3096 emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond));
3099 void Assembler::vcvt_f64_f32(const DwVfpRegister dst, const SwVfpRegister src,
3102 emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond));
3105 void Assembler::vcvt_f32_f64(const SwVfpRegister dst, const DwVfpRegister src,
3107 DCHECK(VfpRegisterIsAvailable(src));
3108 emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond));
3128 void Assembler::vneg(const DwVfpRegister dst, const DwVfpRegister src,
3134 DCHECK(VfpRegisterIsAvailable(src));
3138 src.split_code(&vm, &m);
3144 void Assembler::vneg(const SwVfpRegister dst, const SwVfpRegister src,
3152 src.split_code(&vm, &m);
3158 void Assembler::vabs(const DwVfpRegister dst, const DwVfpRegister src,
3164 DCHECK(VfpRegisterIsAvailable(src));
3168 src.split_code(&vm, &m);
3173 void Assembler::vabs(const SwVfpRegister dst, const SwVfpRegister src,
3181 src.split_code(&vm, &m);
3585 void Assembler::vsqrt(const DwVfpRegister dst, const DwVfpRegister src,
3591 DCHECK(VfpRegisterIsAvailable(src));
3595 src.split_code(&vm, &m);
3600 void Assembler::vsqrt(const SwVfpRegister dst, const SwVfpRegister src,
3608 src.split_code(&vm, &m);
3627 void Assembler::vrinta(const SwVfpRegister dst, const SwVfpRegister src) {
3635 src.split_code(&vm, &m);
3640 void Assembler::vrinta(const DwVfpRegister dst, const DwVfpRegister src) {
3648 src.split_code(&vm, &m);
3653 void Assembler::vrintn(const SwVfpRegister dst, const SwVfpRegister src) {
3661 src.split_code(&vm, &m);
3666 void Assembler::vrintn(const DwVfpRegister dst, const DwVfpRegister src) {
3674 src.split_code(&vm, &m);
3679 void Assembler::vrintp(const SwVfpRegister dst, const SwVfpRegister src) {
3687 src.split_code(&vm, &m);
3692 void Assembler::vrintp(const DwVfpRegister dst, const DwVfpRegister src) {
3700 src.split_code(&vm, &m);
3705 void Assembler::vrintm(const SwVfpRegister dst, const SwVfpRegister src) {
3713 src.split_code(&vm, &m);
3718 void Assembler::vrintm(const DwVfpRegister dst, const DwVfpRegister src) {
3726 src.split_code(&vm, &m);
3731 void Assembler::vrintz(const SwVfpRegister dst, const SwVfpRegister src,
3739 src.split_code(&vm, &m);
3744 void Assembler::vrintz(const DwVfpRegister dst, const DwVfpRegister src,
3752 src.split_code(&vm, &m);
3760 const NeonMemOperand& src) {
3767 emit(0xFU * B28 | 4 * B24 | d * B22 | 2 * B20 | src.rn().code() * B16 |
3768 vd * B12 | dst.type() * B8 | size * B6 | src.align() * B4 |
3769 src.rm().code());
3774 const NeonMemOperand& src) {
3790 src.rn().code() * B16 | vd * B12 | size * B10 | index_align * B4 |
3791 src.rm().code());
3796 const NeonMemOperand& src) {
3801 src.rn().code() * B16 | vd * B12 | 0xC * B8 | size * B6 |
3802 dst.length() * B5 | src.rm().code());
3805 void Assembler::vst1(NeonSize size, const NeonListOperand& src,
3812 src.base().split_code(&vd, &d);
3814 src.type() * B8 | size * B6 | dst.align() * B4 | dst.rm().code());
3817 void Assembler::vst1s(NeonSize size, const NeonListOperand& src, uint8_t index,
3828 src.base().split_code(&vd, &d);
3833 void Assembler::vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src) {
3841 src.split_code(&vm, &m);
3849 DwVfpRegister dst, QwNeonRegister src) {
3858 src.split_code(&vm, &m);
3892 Register src) {
3899 emit(0xEEu * B24 | vd * B16 | src.code() * B12 | 0xB * B8 | d * B7 | B4 |
3903 void Assembler::vmov(NeonDataType dt, Register dst, DwVfpRegister src,
3909 src.split_code(&vn, &n);
3917 void Assembler::vmov(QwNeonRegister dst, QwNeonRegister src) {
3920 vorr(dst, src, src);
3923 void Assembler::vdup(NeonSize size, QwNeonRegister dst, Register src) {
3942 emit(al | 0x1D * B23 | B * B22 | B21 | vd * B16 | src.code() * B12 |
3959 DwVfpRegister src, int index) {
3969 src.split_code(&vm, &m);
3975 void Assembler::vdup(NeonSize size, DwVfpRegister dst, DwVfpRegister src,
3979 emit(EncodeNeonDupOp(size, NEON_D, dst.code(), src, index));
3982 void Assembler::vdup(NeonSize size, QwNeonRegister dst, DwVfpRegister src,
3986 emit(EncodeNeonDupOp(size, NEON_Q, dst.code(), src, index));
3991 VFPType src_type, QwNeonRegister src) {
3998 src.split_code(&vm, &m);
4013 void Assembler::vcvt_f32_s32(QwNeonRegister dst, QwNeonRegister src) {
4016 DCHECK(VfpRegisterIsAvailable(src));
4017 emit(EncodeNeonVCVT(F32, dst, S32, src));
4020 void Assembler::vcvt_f32_u32(QwNeonRegister dst, QwNeonRegister src) {
4023 DCHECK(VfpRegisterIsAvailable(src));
4024 emit(EncodeNeonVCVT(F32, dst, U32, src));
4027 void Assembler::vcvt_s32_f32(QwNeonRegister dst, QwNeonRegister src) {
4030 DCHECK(VfpRegisterIsAvailable(src));
4031 emit(EncodeNeonVCVT(S32, dst, F32, src));
4034 void Assembler::vcvt_u32_f32(QwNeonRegister dst, QwNeonRegister src) {
4037 DCHECK(VfpRegisterIsAvailable(src));
4038 emit(EncodeNeonVCVT(U32, dst, F32, src));
4168 void Assembler::vmvn(QwNeonRegister dst, QwNeonRegister src) {
4172 emit(EncodeNeonUnaryOp(VMVN, NEON_Q, Neon8, dst.code(), src.code()));
4175 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) {
4180 emit(EncodeNeonUnaryOp(VSWP, NEON_D, Neon8, dst.code(), src.code()));
4183 void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) {
4187 emit(EncodeNeonUnaryOp(VSWP, NEON_Q, Neon8, dst.code(), src.code()));
4190 void Assembler::vabs(QwNeonRegister dst, QwNeonRegister src) {
4194 emit(EncodeNeonUnaryOp(VABSF, NEON_Q, Neon32, dst.code(), src.code()));
4197 void Assembler::vabs(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
4201 emit(EncodeNeonUnaryOp(VABS, NEON_Q, size, dst.code(), src.code()));
4204 void Assembler::vneg(QwNeonRegister dst, QwNeonRegister src) {
4208 emit(EncodeNeonUnaryOp(VNEGF, NEON_Q, Neon32, dst.code(), src.code()));
4211 void Assembler::vneg(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
4215 emit(EncodeNeonUnaryOp(VNEG, NEON_Q, size, dst.code(), src.code()));
4673 void Assembler::vshl(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src,
4679 dst.code(), src.code(), shift));
4682 void Assembler::vshl(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src,
4687 emit(EncodeNeonShiftRegisterOp(VSHL, dt, NEON_Q, dst.code(), src.code(),
4691 void Assembler::vshr(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src,
4697 dst.code(), src.code(), shift));
4700 void Assembler::vshr(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src,
4706 dst.code(), src.code(), shift));
4709 void Assembler::vsli(NeonSize size, DwVfpRegister dst, DwVfpRegister src,
4714 emit(EncodeNeonShiftOp(VSLI, size, false, NEON_D, dst.code(), src.code(),
4718 void Assembler::vsri(NeonSize size, DwVfpRegister dst, DwVfpRegister src,
4723 emit(EncodeNeonShiftOp(VSRI, size, false, NEON_D, dst.code(), src.code(),
4727 void Assembler::vsra(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src,
4733 dst.code(), src.code(), imm));
4736 void Assembler::vrecpe(QwNeonRegister dst, QwNeonRegister src) {
4740 emit(EncodeNeonUnaryOp(VRECPE, NEON_Q, Neon32, dst.code(), src.code()));
4743 void Assembler::vrsqrte(QwNeonRegister dst, QwNeonRegister src) {
4747 emit(EncodeNeonUnaryOp(VRSQRTE, NEON_Q, Neon32, dst.code(), src.code()));
4838 const QwNeonRegister src) {
4842 emit(EncodeNeonUnaryOp(VRINTM, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4846 const QwNeonRegister src) {
4850 emit(EncodeNeonUnaryOp(VRINTN, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4854 const QwNeonRegister src) {
4858 emit(EncodeNeonUnaryOp(VRINTP, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4862 const QwNeonRegister src) {
4866 emit(EncodeNeonUnaryOp(VRINTZ, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4934 void Assembler::vclt(NeonSize size, QwNeonRegister dst, QwNeonRegister src,
4940 emit(EncodeNeonUnaryOp(VCLT0, NEON_Q, size, dst.code(), src.code()));
5003 void Assembler::vrev16(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
5007 emit(EncodeNeonUnaryOp(VREV16, NEON_Q, size, dst.code(), src.code()));
5010 void Assembler::vrev32(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
5014 emit(EncodeNeonUnaryOp(VREV32, NEON_Q, size, dst.code(), src.code()));
5017 void Assembler::vrev64(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
5021 emit(EncodeNeonUnaryOp(VREV64, NEON_Q, size, dst.code(), src.code()));
5039 QwNeonRegister src) {
5043 NeonDataTypeToSize(dt), dst.code(), src.code()));
5047 QwNeonRegister src) {
5051 NeonDataTypeToSize(dt), dst.code(), src.code()));
5061 void Assembler::vcnt(QwNeonRegister dst, QwNeonRegister src) {
5065 emit(EncodeNeonUnaryOp(VCNT, NEON_Q, Neon8, dst.code(), src.code()));