Lines Matching refs:dst
827 Register dst =
831 DCHECK(IsNop(instr_at(pos + kInstrSize), dst.code()));
833 DCHECK(IsNop(instr_at(pos + 2 * kInstrSize), dst.code()));
838 // movw dst, #target16_0
839 // movt dst, #target16_1
841 // mov dst, #target8_0
842 // orr dst, dst, #target8_1 << 8
843 // orr dst, dst, #target8_2 << 16
852 patcher.mov(dst, Operand(target24));
862 patcher.movw(dst, target16_0);
867 patcher.movw(dst, target16_0);
868 patcher.movt(dst, target16_1);
878 patcher.mov(dst, Operand(target8_0));
879 patcher.orr(dst, dst, Operand(target8_1 << 8));
883 patcher.mov(dst, Operand(target8_0));
884 patcher.orr(dst, dst, Operand(target8_1 << 8));
885 patcher.orr(dst, dst, Operand(target8_2 << 16));
1536 void Assembler::and_(Register dst, Register src1, const Operand& src2, SBit s,
1538 AddrMode1(cond | AND | s, dst, src1, src2);
1541 void Assembler::and_(Register dst, Register src1, Register src2, SBit s,
1543 and_(dst, src1, Operand(src2), s, cond);
1546 void Assembler::eor(Register dst, Register src1, const Operand& src2, SBit s,
1548 AddrMode1(cond | EOR | s, dst, src1, src2);
1551 void Assembler::eor(Register dst, Register src1, Register src2, SBit s,
1553 AddrMode1(cond | EOR | s, dst, src1, Operand(src2));
1556 void Assembler::sub(Register dst, Register src1, const Operand& src2, SBit s,
1558 AddrMode1(cond | SUB | s, dst, src1, src2);
1561 void Assembler::sub(Register dst, Register src1, Register src2, SBit s,
1563 sub(dst, src1, Operand(src2), s, cond);
1566 void Assembler::rsb(Register dst, Register src1, const Operand& src2, SBit s,
1568 AddrMode1(cond | RSB | s, dst, src1, src2);
1571 void Assembler::add(Register dst, Register src1, const Operand& src2, SBit s,
1573 AddrMode1(cond | ADD | s, dst, src1, src2);
1576 void Assembler::add(Register dst, Register src1, Register src2, SBit s,
1578 add(dst, src1, Operand(src2), s, cond);
1581 void Assembler::adc(Register dst, Register src1, const Operand& src2, SBit s,
1583 AddrMode1(cond | ADC | s, dst, src1, src2);
1586 void Assembler::sbc(Register dst, Register src1, const Operand& src2, SBit s,
1588 AddrMode1(cond | SBC | s, dst, src1, src2);
1591 void Assembler::rsc(Register dst, Register src1, const Operand& src2, SBit s,
1593 AddrMode1(cond | RSC | s, dst, src1, src2);
1626 void Assembler::orr(Register dst, Register src1, const Operand& src2, SBit s,
1628 AddrMode1(cond | ORR | s, dst, src1, src2);
1631 void Assembler::orr(Register dst, Register src1, Register src2, SBit s,
1633 orr(dst, src1, Operand(src2), s, cond);
1636 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
1639 DCHECK(!(src.IsRegister() && src.rm() == dst && s == LeaveCC && cond == al));
1640 AddrMode1(cond | MOV | s, dst, no_reg, src);
1643 void Assembler::mov(Register dst, Register src, SBit s, Condition cond) {
1644 mov(dst, Operand(src), s, cond);
1647 void Assembler::mov_label_offset(Register dst, Label* label) {
1649 mov(dst, Operand(label->pos() + (Code::kHeaderSize - kHeapObjectTag)));
1667 // mov dst, dst
1670 // mov dst, dst
1671 // mov dst, dst
1678 nop(dst.code());
1680 nop(dst.code());
1695 void Assembler::bic(Register dst, Register src1, const Operand& src2, SBit s,
1697 AddrMode1(cond | BIC | s, dst, src1, src2);
1700 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
1701 AddrMode1(cond | MVN | s, dst, no_reg, src);
1704 void Assembler::asr(Register dst, Register src1, const Operand& src2, SBit s,
1707 mov(dst, Operand(src1, ASR, src2.rm()), s, cond);
1709 mov(dst, Operand(src1, ASR, src2.immediate()), s, cond);
1713 void Assembler::lsl(Register dst, Register src1, const Operand& src2, SBit s,
1716 mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
1718 mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
1722 void Assembler::lsr(Register dst, Register src1, const Operand& src2, SBit s,
1725 mov(dst, Operand(src1, LSR, src2.rm()), s, cond);
1727 mov(dst, Operand(src1, LSR, src2.immediate()), s, cond);
1732 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
1734 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1735 emit(cond | A | s | dst.code() * B16 | srcA.code() * B12 | src2.code() * B8 |
1739 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
1741 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1743 emit(cond | B22 | B21 | dst.code() * B16 | srcA.code() * B12 |
1747 void Assembler::sdiv(Register dst, Register src1, Register src2,
1749 DCHECK(dst != pc && src1 != pc && src2 != pc);
1751 emit(cond | B26 | B25 | B24 | B20 | dst.code() * B16 | 0xF * B12 |
1755 void Assembler::udiv(Register dst, Register src1, Register src2,
1757 DCHECK(dst != pc && src1 != pc && src2 != pc);
1759 emit(cond | B26 | B25 | B24 | B21 | B20 | dst.code() * B16 | 0xF * B12 |
1763 void Assembler::mul(Register dst, Register src1, Register src2, SBit s,
1765 DCHECK(dst != pc && src1 != pc && src2 != pc);
1766 // dst goes in bits 16-19 for this instruction!
1767 emit(cond | s | dst.code() * B16 | src2.code() * B8 | B7 | B4 | src1.code());
1770 void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA,
1772 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1773 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 |
1777 void Assembler::smmul(Register dst, Register src1, Register src2,
1779 DCHECK(dst != pc && src1 != pc && src2 != pc);
1780 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | 0xF * B12 |
1817 void Assembler::clz(Register dst, Register src, Condition cond) {
1818 DCHECK(dst != pc && src != pc);
1819 emit(cond | B24 | B22 | B21 | 15 * B16 | dst.code() * B12 | 15 * B8 | CLZ |
1826 void Assembler::usat(Register dst, int satpos, const Operand& src,
1828 DCHECK(dst != pc && src.rm_ != pc);
1838 emit(cond | 0x6 * B24 | 0xE * B20 | satpos * B16 | dst.code() * B12 |
1847 // ubfx dst, src, #lsb, #width
1848 void Assembler::ubfx(Register dst, Register src, int lsb, int width,
1851 DCHECK(dst != pc && src != pc);
1854 emit(cond | 0xF * B23 | B22 | B21 | (width - 1) * B16 | dst.code() * B12 |
1862 // sbfx dst, src, #lsb, #width
1863 void Assembler::sbfx(Register dst, Register src, int lsb, int width,
1866 DCHECK(dst != pc && src != pc);
1869 emit(cond | 0xF * B23 | B21 | (width - 1) * B16 | dst.code() * B12 |
1876 // bfc dst, #lsb, #width
1877 void Assembler::bfc(Register dst, int lsb, int width, Condition cond) {
1879 DCHECK(dst != pc);
1883 emit(cond | 0x1F * B22 | msb * B16 | dst.code() * B12 | lsb * B7 | B4 | 0xF);
1889 // bfi dst, src, #lsb, #width
1890 void Assembler::bfi(Register dst, Register src, int lsb, int width,
1893 DCHECK(dst != pc && src != pc);
1897 emit(cond | 0x1F * B22 | msb * B16 | dst.code() * B12 | lsb * B7 | B4 |
1901 void Assembler::pkhbt(Register dst, Register src1, const Operand& src2,
1906 DCHECK(dst != pc);
1912 emit(cond | 0x68 * B20 | src1.code() * B16 | dst.code() * B12 |
1916 void Assembler::pkhtb(Register dst, Register src1, const Operand& src2,
1921 DCHECK(dst != pc);
1928 emit(cond | 0x68 * B20 | src1.code() * B16 | dst.code() * B12 | asr * B7 |
1932 void Assembler::sxtb(Register dst, Register src, int rotate, Condition cond) {
1936 DCHECK(dst != pc);
1939 emit(cond | 0x6A * B20 | 0xF * B16 | dst.code() * B12 |
1943 void Assembler::sxtab(Register dst, Register src1, Register src2, int rotate,
1948 DCHECK(dst != pc);
1952 emit(cond | 0x6A * B20 | src1.code() * B16 | dst.code() * B12 |
1956 void Assembler::sxth(Register dst, Register src, int rotate, Condition cond) {
1960 DCHECK(dst != pc);
1963 emit(cond | 0x6B * B20 | 0xF * B16 | dst.code() * B12 |
1967 void Assembler::sxtah(Register dst, Register src1, Register src2, int rotate,
1972 DCHECK(dst != pc);
1976 emit(cond | 0x6B * B20 | src1.code() * B16 | dst.code() * B12 |
1980 void Assembler::uxtb(Register dst, Register src, int rotate, Condition cond) {
1984 DCHECK(dst != pc);
1987 emit(cond | 0x6E * B20 | 0xF * B16 | dst.code() * B12 |
1991 void Assembler::uxtab(Register dst, Register src1, Register src2, int rotate,
1996 DCHECK(dst != pc);
2000 emit(cond | 0x6E * B20 | src1.code() * B16 | dst.code() * B12 |
2004 void Assembler::uxtb16(Register dst, Register src, int rotate, Condition cond) {
2008 DCHECK(dst != pc);
2011 emit(cond | 0x6C * B20 | 0xF * B16 | dst.code() * B12 |
2015 void Assembler::uxth(Register dst, Register src, int rotate, Condition cond) {
2019 DCHECK(dst != pc);
2022 emit(cond | 0x6F * B20 | 0xF * B16 | dst.code() * B12 |
2026 void Assembler::uxtah(Register dst, Register src1, Register src2, int rotate,
2031 DCHECK(dst != pc);
2035 emit(cond | 0x6F * B20 | src1.code() * B16 | dst.code() * B12 |
2039 void Assembler::rbit(Register dst, Register src, Condition cond) {
2043 DCHECK(dst != pc);
2045 emit(cond | 0x6FF * B16 | dst.code() * B12 | 0xF3 * B4 | src.code());
2048 void Assembler::rev(Register dst, Register src, Condition cond) {
2051 DCHECK(dst != pc);
2053 emit(cond | 0x6BF * B16 | dst.code() * B12 | 0xF3 * B4 | src.code());
2057 void Assembler::mrs(Register dst, SRegister s, Condition cond) {
2058 DCHECK(dst != pc);
2059 emit(cond | B24 | s | 15 * B16 | dst.code() * B12);
2090 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
2091 AddrMode2(cond | B26 | L, dst, src);
2094 void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
2095 AddrMode2(cond | B26, src, dst);
2098 void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
2099 AddrMode2(cond | B26 | B | L, dst, src);
2102 void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
2103 AddrMode2(cond | B26 | B, src, dst);
2106 void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
2107 AddrMode3(cond | L | B7 | H | B4, dst, src);
2110 void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
2111 AddrMode3(cond | B7 | H | B4, src, dst);
2114 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
2115 AddrMode3(cond | L | B7 | S6 | B4, dst, src);
2118 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
2119 AddrMode3(cond | L | B7 | S6 | H | B4, dst, src);
2131 void Assembler::strd(Register src1, Register src2, const MemOperand& dst,
2133 DCHECK(dst.rm() == no_reg);
2137 AddrMode3(cond | B7 | B6 | B5 | B4, src1, dst);
2140 void Assembler::ldr_pcrel(Register dst, int imm12, Condition cond) {
2147 emit(cond | B26 | am | L | pc.code() * B16 | dst.code() * B12 | imm12);
2151 void Assembler::ldrex(Register dst, Register src, Condition cond) {
2154 DCHECK(dst != pc);
2156 emit(cond | B24 | B23 | B20 | src.code() * B16 | dst.code() * B12 | 0xF9F);
2159 void Assembler::strex(Register src1, Register src2, Register dst,
2164 DCHECK(dst != pc);
2167 DCHECK(src1 != dst);
2169 emit(cond | B24 | B23 | dst.code() * B16 | src1.code() * B12 | 0xF9 * B4 |
2173 void Assembler::ldrexb(Register dst, Register src, Condition cond) {
2176 DCHECK(dst != pc);
2178 emit(cond | B24 | B23 | B22 | B20 | src.code() * B16 | dst.code() * B12 |
2182 void Assembler::strexb(Register src1, Register src2, Register dst,
2187 DCHECK(dst != pc);
2190 DCHECK(src1 != dst);
2192 emit(cond | B24 | B23 | B22 | dst.code() * B16 | src1.code() * B12 |
2196 void Assembler::ldrexh(Register dst, Register src, Condition cond) {
2199 DCHECK(dst != pc);
2202 dst.code() * B12 | 0xF9F);
2205 void Assembler::strexh(Register src1, Register src2, Register dst,
2210 DCHECK(dst != pc);
2213 DCHECK(src1 != dst);
2215 emit(cond | B24 | B23 | B22 | B21 | dst.code() * B16 | src1.code() * B12 |
2231 void Assembler::strexd(Register res, Register src1, Register src2, Register dst,
2239 emit(cond | B24 | B23 | B21 | dst.code() * B16 | res.code() * B12 |
2262 void Assembler::ldm(BlockAddrMode am, Register base, RegList dst,
2265 DCHECK(base == sp || !dst.has(sp));
2267 AddrMode4(cond | B27 | am | L, base, dst);
2270 if (cond == al && dst.has(pc)) {
2425 void Assembler::vldr(const DwVfpRegister dst, const Register base, int offset,
2431 DCHECK(VfpRegisterIsAvailable(dst));
2439 dst.split_code(&vd, &d);
2461 void Assembler::vldr(const DwVfpRegister dst, const MemOperand& operand,
2463 DCHECK(VfpRegisterIsAvailable(dst));
2470 vldr(dst, scratch, 0, cond);
2472 vldr(dst, operand.rn(), operand.offset(), cond);
2476 void Assembler::vldr(const SwVfpRegister dst, const Register base, int offset,
2488 dst.split_code(&sd, &d);
2510 void Assembler::vldr(const SwVfpRegister dst, const MemOperand& operand,
2518 vldr(dst, scratch, 0, cond);
2520 vldr(dst, operand.rn(), operand.offset(), cond);
2726 void Assembler::vmov(const DwVfpRegister dst, uint64_t imm) {
2736 dst.split_code(&vd, &d);
2744 void Assembler::vmov(const QwNeonRegister dst, uint64_t imm) {
2754 dst.split_code(&vd, &d);
2810 void Assembler::vmov(const SwVfpRegister dst, Float32 imm) {
2822 dst.split_code(&vd, &d);
2828 vmov(dst, scratch);
2832 void Assembler::vmov(const DwVfpRegister dst, base::Double imm,
2834 DCHECK(VfpRegisterIsAvailable(dst));
2845 dst.split_code(&vd, &d);
2859 vmov(dst, scratch, scratch);
2863 vmov(NeonS32, dst, 0, scratch);
2870 vmov(NeonS32, dst, 1, scratch);
2876 vmov(dst, scratch, extra_scratch);
2881 void Assembler::vmov(const SwVfpRegister dst, const SwVfpRegister src,
2886 dst.split_code(&sd, &d);
2892 void Assembler::vmov(const DwVfpRegister dst, const DwVfpRegister src,
2898 DCHECK(VfpRegisterIsAvailable(dst));
2901 dst.split_code(&vd, &d);
2908 void Assembler::vmov(const DwVfpRegister dst, const Register src1,
2914 DCHECK(VfpRegisterIsAvailable(dst));
2917 dst.split_code(&vm, &m);
2936 void Assembler::vmov(const SwVfpRegister dst, const Register src,
2944 dst.split_code(&sn, &n);
2948 void Assembler::vmov(const Register dst, const SwVfpRegister src,
2954 DCHECK(dst != pc);
2957 emit(cond | 0xE * B24 | B20 | sn * B16 | dst.code() * B12 | 0xA * B8 |
3055 void Assembler::vcvt_f64_s32(const DwVfpRegister dst, const SwVfpRegister src,
3057 DCHECK(VfpRegisterIsAvailable(dst));
3058 emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond));
3061 void Assembler::vcvt_f32_s32(const SwVfpRegister dst, const SwVfpRegister src,
3063 emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond));
3066 void Assembler::vcvt_f64_u32(const DwVfpRegister dst, const SwVfpRegister src,
3068 DCHECK(VfpRegisterIsAvailable(dst));
3069 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond));
3072 void Assembler::vcvt_f32_u32(const SwVfpRegister dst, const SwVfpRegister src,
3074 emit(EncodeVCVT(F32, dst.code(), U32, src.code(), mode, cond));
3077 void Assembler::vcvt_s32_f32(const SwVfpRegister dst, const SwVfpRegister src,
3079 emit(EncodeVCVT(S32, dst.code(), F32, src.code(), mode, cond));
3082 void Assembler::vcvt_u32_f32(const SwVfpRegister dst, const SwVfpRegister src,
3084 emit(EncodeVCVT(U32, dst.code(), F32, src.code(), mode, cond));
3087 void Assembler::vcvt_s32_f64(const SwVfpRegister dst, const DwVfpRegister src,
3090 emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond));
3093 void Assembler::vcvt_u32_f64(const SwVfpRegister dst, const DwVfpRegister src,
3096 emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond));
3099 void Assembler::vcvt_f64_f32(const DwVfpRegister dst, const SwVfpRegister src,
3101 DCHECK(VfpRegisterIsAvailable(dst));
3102 emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond));
3105 void Assembler::vcvt_f32_f64(const SwVfpRegister dst, const DwVfpRegister src,
3108 emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond));
3111 void Assembler::vcvt_f64_s32(const DwVfpRegister dst, int fraction_bits,
3117 DCHECK(VfpRegisterIsAvailable(dst));
3120 dst.split_code(&vd, &d);
3128 void Assembler::vneg(const DwVfpRegister dst, const DwVfpRegister src,
3133 DCHECK(VfpRegisterIsAvailable(dst));
3136 dst.split_code(&vd, &d);
3144 void Assembler::vneg(const SwVfpRegister dst, const SwVfpRegister src,
3150 dst.split_code(&vd, &d);
3158 void Assembler::vabs(const DwVfpRegister dst, const DwVfpRegister src,
3163 DCHECK(VfpRegisterIsAvailable(dst));
3166 dst.split_code(&vd, &d);
3173 void Assembler::vabs(const SwVfpRegister dst, const SwVfpRegister src,
3179 dst.split_code(&vd, &d);
3186 void Assembler::vadd(const DwVfpRegister dst, const DwVfpRegister src1,
3193 DCHECK(VfpRegisterIsAvailable(dst));
3197 dst.split_code(&vd, &d);
3206 void Assembler::vadd(const SwVfpRegister dst, const SwVfpRegister src1,
3214 dst.split_code(&vd, &d);
3223 void Assembler::vsub(const DwVfpRegister dst, const DwVfpRegister src1,
3230 DCHECK(VfpRegisterIsAvailable(dst));
3234 dst.split_code(&vd, &d);
3243 void Assembler::vsub(const SwVfpRegister dst, const SwVfpRegister src1,
3251 dst.split_code(&vd, &d);
3260 void Assembler::vmul(const DwVfpRegister dst, const DwVfpRegister src1,
3267 DCHECK(VfpRegisterIsAvailable(dst));
3271 dst.split_code(&vd, &d);
3280 void Assembler::vmul(const SwVfpRegister dst, const SwVfpRegister src1,
3288 dst.split_code(&vd, &d);
3297 void Assembler::vmla(const DwVfpRegister dst, const DwVfpRegister src1,
3302 DCHECK(VfpRegisterIsAvailable(dst));
3306 dst.split_code(&vd, &d);
3315 void Assembler::vmla(const SwVfpRegister dst, const SwVfpRegister src1,
3321 dst.split_code(&vd, &d);
3330 void Assembler::vmls(const DwVfpRegister dst, const DwVfpRegister src1,
3335 DCHECK(VfpRegisterIsAvailable(dst));
3339 dst.split_code(&vd, &d);
3348 void Assembler::vmls(const SwVfpRegister dst, const SwVfpRegister src1,
3354 dst.split_code(&vd, &d);
3363 void Assembler::vdiv(const DwVfpRegister dst, const DwVfpRegister src1,
3370 DCHECK(VfpRegisterIsAvailable(dst));
3374 dst.split_code(&vd, &d);
3383 void Assembler::vdiv(const SwVfpRegister dst, const SwVfpRegister src1,
3391 dst.split_code(&vd, &d);
3457 void Assembler::vmaxnm(const DwVfpRegister dst, const DwVfpRegister src1,
3463 dst.split_code(&vd, &d);
3473 void Assembler::vmaxnm(const SwVfpRegister dst, const SwVfpRegister src1,
3479 dst.split_code(&vd, &d);
3489 void Assembler::vminnm(const DwVfpRegister dst, const DwVfpRegister src1,
3495 dst.split_code(&vd, &d);
3505 void Assembler::vminnm(const SwVfpRegister dst, const SwVfpRegister src1,
3511 dst.split_code(&vd, &d);
3521 void Assembler::vsel(Condition cond, const DwVfpRegister dst,
3528 dst.split_code(&vd, &d);
3553 void Assembler::vsel(Condition cond, const SwVfpRegister dst,
3560 dst.split_code(&vd, &d);
3585 void Assembler::vsqrt(const DwVfpRegister dst, const DwVfpRegister src,
3590 DCHECK(VfpRegisterIsAvailable(dst));
3593 dst.split_code(&vd, &d);
3600 void Assembler::vsqrt(const SwVfpRegister dst, const SwVfpRegister src,
3606 dst.split_code(&vd, &d);
3613 void Assembler::vmsr(Register dst, Condition cond) {
3617 emit(cond | 0xE * B24 | 0xE * B20 | B16 | dst.code() * B12 | 0xA * B8 | B4);
3620 void Assembler::vmrs(Register dst, Condition cond) {
3624 emit(cond | 0xE * B24 | 0xF * B20 | B16 | dst.code() * B12 | 0xA * B8 | B4);
3627 void Assembler::vrinta(const SwVfpRegister dst, const SwVfpRegister src) {
3633 dst.split_code(&vd, &d);
3640 void Assembler::vrinta(const DwVfpRegister dst, const DwVfpRegister src) {
3646 dst.split_code(&vd, &d);
3653 void Assembler::vrintn(const SwVfpRegister dst, const SwVfpRegister src) {
3659 dst.split_code(&vd, &d);
3666 void Assembler::vrintn(const DwVfpRegister dst, const DwVfpRegister src) {
3672 dst.split_code(&vd, &d);
3679 void Assembler::vrintp(const SwVfpRegister dst, const SwVfpRegister src) {
3685 dst.split_code(&vd, &d);
3692 void Assembler::vrintp(const DwVfpRegister dst, const DwVfpRegister src) {
3698 dst.split_code(&vd, &d);
3705 void Assembler::vrintm(const SwVfpRegister dst, const SwVfpRegister src) {
3711 dst.split_code(&vd, &d);
3718 void Assembler::vrintm(const DwVfpRegister dst, const DwVfpRegister src) {
3724 dst.split_code(&vd, &d);
3731 void Assembler::vrintz(const SwVfpRegister dst, const SwVfpRegister src,
3737 dst.split_code(&vd, &d);
3744 void Assembler::vrintz(const DwVfpRegister dst, const DwVfpRegister src,
3750 dst.split_code(&vd, &d);
3759 void Assembler::vld1(NeonSize size, const NeonListOperand& dst,
3766 dst.base().split_code(&vd, &d);
3768 vd * B12 | dst.type() * B8 | size * B6 | src.align() * B4 |
3773 void Assembler::vld1s(NeonSize size, const NeonListOperand& dst, uint8_t index,
3788 dst.base().split_code(&vd, &d);
3795 void Assembler::vld1r(NeonSize size, const NeonListOperand& dst,
3799 dst.base().split_code(&vd, &d);
3802 dst.length() * B5 | src.rm().code());
3806 const NeonMemOperand& dst) {
3813 emit(0xFU * B28 | 4 * B24 | d * B22 | dst.rn().code() * B16 | vd * B12 |
3814 src.type() * B8 | size * B6 | dst.align() * B4 | dst.rm().code());
3818 const NeonMemOperand& dst) {
3829 emit(0xFU * B28 | 9 * B23 | d * B22 | dst.rn().code() * B16 | vd * B12 |
3830 size * B10 | index_align * B4 | dst.rm().code());
3833 void Assembler::vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src) {
3839 dst.split_code(&vd, &d);
3849 DwVfpRegister dst, QwNeonRegister src) {
3856 dst.split_code(&vd, &d);
3891 void Assembler::vmov(NeonDataType dt, DwVfpRegister dst, int index,
3897 dst.split_code(&vd, &d);
3903 void Assembler::vmov(NeonDataType dt, Register dst, DwVfpRegister src,
3913 emit(0xEEu * B24 | u * B23 | B20 | vn * B16 | dst.code() * B12 | 0xB * B8 |
3917 void Assembler::vmov(QwNeonRegister dst, QwNeonRegister src) {
3920 vorr(dst, src, src);
3923 void Assembler::vdup(NeonSize size, QwNeonRegister dst, Register src) {
3940 dst.split_code(&vd, &d);
3975 void Assembler::vdup(NeonSize size, DwVfpRegister dst, DwVfpRegister src,
3979 emit(EncodeNeonDupOp(size, NEON_D, dst.code(), src, index));
3982 void Assembler::vdup(NeonSize size, QwNeonRegister dst, DwVfpRegister src,
3986 emit(EncodeNeonDupOp(size, NEON_Q, dst.code(), src, index));
3990 static Instr EncodeNeonVCVT(VFPType dst_type, QwNeonRegister dst,
3996 dst.split_code(&vd, &d);
4013 void Assembler::vcvt_f32_s32(QwNeonRegister dst, QwNeonRegister src) {
4015 DCHECK(VfpRegisterIsAvailable(dst));
4017 emit(EncodeNeonVCVT(F32, dst, S32, src));
4020 void Assembler::vcvt_f32_u32(QwNeonRegister dst, QwNeonRegister src) {
4022 DCHECK(VfpRegisterIsAvailable(dst));
4024 emit(EncodeNeonVCVT(F32, dst, U32, src));
4027 void Assembler::vcvt_s32_f32(QwNeonRegister dst, QwNeonRegister src) {
4029 DCHECK(VfpRegisterIsAvailable(dst));
4031 emit(EncodeNeonVCVT(S32, dst, F32, src));
4034 void Assembler::vcvt_u32_f32(QwNeonRegister dst, QwNeonRegister src) {
4036 DCHECK(VfpRegisterIsAvailable(dst));
4038 emit(EncodeNeonVCVT(U32, dst, F32, src));
4168 void Assembler::vmvn(QwNeonRegister dst, QwNeonRegister src) {
4172 emit(EncodeNeonUnaryOp(VMVN, NEON_Q, Neon8, dst.code(), src.code()));
4175 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) {
4180 emit(EncodeNeonUnaryOp(VSWP, NEON_D, Neon8, dst.code(), src.code()));
4183 void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) {
4187 emit(EncodeNeonUnaryOp(VSWP, NEON_Q, Neon8, dst.code(), src.code()));
4190 void Assembler::vabs(QwNeonRegister dst, QwNeonRegister src) {
4194 emit(EncodeNeonUnaryOp(VABSF, NEON_Q, Neon32, dst.code(), src.code()));
4197 void Assembler::vabs(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
4201 emit(EncodeNeonUnaryOp(VABS, NEON_Q, size, dst.code(), src.code()));
4204 void Assembler::vneg(QwNeonRegister dst, QwNeonRegister src) {
4208 emit(EncodeNeonUnaryOp(VNEGF, NEON_Q, Neon32, dst.code(), src.code()));
4211 void Assembler::vneg(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
4215 emit(EncodeNeonUnaryOp(VNEG, NEON_Q, size, dst.code(), src.code()));
4263 void Assembler::vand(QwNeonRegister dst, QwNeonRegister src1,
4268 emit(EncodeNeonBinaryBitwiseOp(VAND, NEON_Q, dst.code(), src1.code(),
4272 void Assembler::vbic(QwNeonRegister dst, QwNeonRegister src1,
4277 emit(EncodeNeonBinaryBitwiseOp(VBIC, NEON_Q, dst.code(), src1.code(),
4281 void Assembler::vbsl(QwNeonRegister dst, QwNeonRegister src1,
4286 emit(EncodeNeonBinaryBitwiseOp(VBSL, NEON_Q, dst.code(), src1.code(),
4290 void Assembler::veor(DwVfpRegister dst, DwVfpRegister src1,
4295 emit(EncodeNeonBinaryBitwiseOp(VEOR, NEON_D, dst.code(), src1.code(),
4299 void Assembler::veor(QwNeonRegister dst, QwNeonRegister src1,
4304 emit(EncodeNeonBinaryBitwiseOp(VEOR, NEON_Q, dst.code(), src1.code(),
4308 void Assembler::vorr(QwNeonRegister dst, QwNeonRegister src1,
4313 emit(EncodeNeonBinaryBitwiseOp(VORR, NEON_Q, dst.code(), src1.code(),
4317 void Assembler::vorn(QwNeonRegister dst, QwNeonRegister src1,
4322 emit(EncodeNeonBinaryBitwiseOp(VORN, NEON_Q, dst.code(), src1.code(),
4339 static Instr EncodeNeonBinOp(FPBinOp op, QwNeonRegister dst,
4377 dst.split_code(&vd, &d);
4403 QwNeonRegister dst, QwNeonRegister src1,
4450 dst.split_code(&vd, &d);
4461 static Instr EncodeNeonBinOp(IntegerBinOp op, NeonSize size, QwNeonRegister dst,
4465 return EncodeNeonBinOp(op, static_cast<NeonDataType>(size), dst, src1, src2);
4468 void Assembler::vadd(QwNeonRegister dst, QwNeonRegister src1,
4473 emit(EncodeNeonBinOp(VADDF, dst, src1, src2));
4476 void Assembler::vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4481 emit(EncodeNeonBinOp(VADD, size, dst, src1, src2));
4484 void Assembler::vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4489 emit(EncodeNeonBinOp(VQADD, dt, dst, src1, src2));
4492 void Assembler::vsub(QwNeonRegister dst, QwNeonRegister src1,
4497 emit(EncodeNeonBinOp(VSUBF, dst, src1, src2));
4500 void Assembler::vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4505 emit(EncodeNeonBinOp(VSUB, size, dst, src1, src2));
4508 void Assembler::vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4513 emit(EncodeNeonBinOp(VQSUB, dt, dst, src1, src2));
4516 void Assembler::vmlal(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
4522 dst.split_code(&vd, &d);
4535 void Assembler::vmul(QwNeonRegister dst, QwNeonRegister src1,
4540 emit(EncodeNeonBinOp(VMULF, dst, src1, src2));
4543 void Assembler::vmul(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4548 emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2));
4551 void Assembler::vmull(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
4557 dst.split_code(&vd, &d);
4568 void Assembler::vmin(QwNeonRegister dst, QwNeonRegister src1,
4573 emit(EncodeNeonBinOp(VMINF, dst, src1, src2));
4576 void Assembler::vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4581 emit(EncodeNeonBinOp(VMIN, dt, dst, src1, src2));
4584 void Assembler::vmax(QwNeonRegister dst, QwNeonRegister src1,
4589 emit(EncodeNeonBinOp(VMAXF, dst, src1, src2));
4592 void Assembler::vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4597 emit(EncodeNeonBinOp(VMAX, dt, dst, src1, src2));
4673 void Assembler::vshl(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src,
4679 dst.code(), src.code(), shift));
4682 void Assembler::vshl(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src,
4687 emit(EncodeNeonShiftRegisterOp(VSHL, dt, NEON_Q, dst.code(), src.code(),
4691 void Assembler::vshr(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src,
4697 dst.code(), src.code(), shift));
4700 void Assembler::vshr(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src,
4706 dst.code(), src.code(), shift));
4709 void Assembler::vsli(NeonSize size, DwVfpRegister dst, DwVfpRegister src,
4714 emit(EncodeNeonShiftOp(VSLI, size, false, NEON_D, dst.code(), src.code(),
4718 void Assembler::vsri(NeonSize size, DwVfpRegister dst, DwVfpRegister src,
4723 emit(EncodeNeonShiftOp(VSRI, size, false, NEON_D, dst.code(), src.code(),
4727 void Assembler::vsra(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src,
4733 dst.code(), src.code(), imm));
4736 void Assembler::vrecpe(QwNeonRegister dst, QwNeonRegister src) {
4740 emit(EncodeNeonUnaryOp(VRECPE, NEON_Q, Neon32, dst.code(), src.code()));
4743 void Assembler::vrsqrte(QwNeonRegister dst, QwNeonRegister src) {
4747 emit(EncodeNeonUnaryOp(VRSQRTE, NEON_Q, Neon32, dst.code(), src.code()));
4750 void Assembler::vrecps(QwNeonRegister dst, QwNeonRegister src1,
4755 emit(EncodeNeonBinOp(VRECPS, dst, src1, src2));
4758 void Assembler::vrsqrts(QwNeonRegister dst, QwNeonRegister src1,
4763 emit(EncodeNeonBinOp(VRSQRTS, dst, src1, src2));
4769 DwVfpRegister dst, DwVfpRegister src1,
4786 dst.split_code(&vd, &d);
4797 void Assembler::vpadd(DwVfpRegister dst, DwVfpRegister src1,
4803 dst.split_code(&vd, &d);
4813 void Assembler::vpadd(NeonSize size, DwVfpRegister dst, DwVfpRegister src1,
4818 emit(EncodeNeonPairwiseOp(VPADD, NeonSizeToDataType(size), dst, src1, src2));
4821 void Assembler::vpmin(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1,
4826 emit(EncodeNeonPairwiseOp(VPMIN, dt, dst, src1, src2));
4829 void Assembler::vpmax(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1,
4834 emit(EncodeNeonPairwiseOp(VPMAX, dt, dst, src1, src2));
4837 void Assembler::vrintm(NeonDataType dt, const QwNeonRegister dst,
4842 emit(EncodeNeonUnaryOp(VRINTM, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4845 void Assembler::vrintn(NeonDataType dt, const QwNeonRegister dst,
4850 emit(EncodeNeonUnaryOp(VRINTN, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4853 void Assembler::vrintp(NeonDataType dt, const QwNeonRegister dst,
4858 emit(EncodeNeonUnaryOp(VRINTP, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4861 void Assembler::vrintz(NeonDataType dt, const QwNeonRegister dst,
4866 emit(EncodeNeonUnaryOp(VRINTZ, NEON_Q, NeonSize(dt), dst.code(), src.code()));
4869 void Assembler::vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4874 emit(EncodeNeonBinOp(VTST, size, dst, src1, src2));
4877 void Assembler::vceq(QwNeonRegister dst, QwNeonRegister src1,
4882 emit(EncodeNeonBinOp(VCEQF, dst, src1, src2));
4885 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4890 emit(EncodeNeonBinOp(VCEQ, size, dst, src1, src2));
4893 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4899 emit(EncodeNeonUnaryOp(VCEQ0, NEON_Q, size, dst.code(), src1.code()));
4902 void Assembler::vcge(QwNeonRegister dst, QwNeonRegister src1,
4907 emit(EncodeNeonBinOp(VCGEF, dst, src1, src2));
4910 void Assembler::vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4915 emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2));
4918 void Assembler::vcgt(QwNeonRegister dst, QwNeonRegister src1,
4923 emit(EncodeNeonBinOp(VCGTF, dst, src1, src2));
4926 void Assembler::vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4931 emit(EncodeNeonBinOp(VCGT, dt, dst, src1, src2));
4934 void Assembler::vclt(NeonSize size, QwNeonRegister dst, QwNeonRegister src,
4940 emit(EncodeNeonUnaryOp(VCLT0, NEON_Q, size, dst.code(), src.code()));
4943 void Assembler::vrhadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4948 emit(EncodeNeonBinOp(VRHADD, dt, dst, src1, src2));
4951 void Assembler::vext(QwNeonRegister dst, QwNeonRegister src1,
4957 dst.split_code(&vd, &d);
5003 void Assembler::vrev16(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
5007 emit(EncodeNeonUnaryOp(VREV16, NEON_Q, size, dst.code(), src.code()));
5010 void Assembler::vrev32(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
5014 emit(EncodeNeonUnaryOp(VREV32, NEON_Q, size, dst.code(), src.code()));
5017 void Assembler::vrev64(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
5021 emit(EncodeNeonUnaryOp(VREV64, NEON_Q, size, dst.code(), src.code()));
5038 void Assembler::vpadal(NeonDataType dt, QwNeonRegister dst,
5043 NeonDataTypeToSize(dt), dst.code(), src.code()));
5046 void Assembler::vpaddl(NeonDataType dt, QwNeonRegister dst,
5051 NeonDataTypeToSize(dt), dst.code(), src.code()));
5054 void Assembler::vqrdmulh(NeonDataType dt, QwNeonRegister dst,
5058 emit(EncodeNeonBinOp(VQRDMULH, dt, dst, src1, src2));
5061 void Assembler::vcnt(QwNeonRegister dst, QwNeonRegister src) {
5065 emit(EncodeNeonUnaryOp(VCNT, NEON_Q, Neon8, dst.code(), src.code()));
5069 static Instr EncodeNeonVTB(DwVfpRegister dst, const NeonListOperand& list,
5076 dst.split_code(&vd, &d);
5086 void Assembler::vtbl(DwVfpRegister dst, const NeonListOperand& list,
5089 emit(EncodeNeonVTB(dst, list, index, false));
5092 void Assembler::vtbx(DwVfpRegister dst, const NeonListOperand& list,
5095 emit(EncodeNeonVTB(dst, list, index, true));