Lines Matching defs:src2
1536 void Assembler::and_(Register dst, Register src1, const Operand& src2, SBit s,
1538 AddrMode1(cond | AND | s, dst, src1, src2);
1541 void Assembler::and_(Register dst, Register src1, Register src2, SBit s,
1543 and_(dst, src1, Operand(src2), s, cond);
1546 void Assembler::eor(Register dst, Register src1, const Operand& src2, SBit s,
1548 AddrMode1(cond | EOR | s, dst, src1, src2);
1551 void Assembler::eor(Register dst, Register src1, Register src2, SBit s,
1553 AddrMode1(cond | EOR | s, dst, src1, Operand(src2));
1556 void Assembler::sub(Register dst, Register src1, const Operand& src2, SBit s,
1558 AddrMode1(cond | SUB | s, dst, src1, src2);
1561 void Assembler::sub(Register dst, Register src1, Register src2, SBit s,
1563 sub(dst, src1, Operand(src2), s, cond);
1566 void Assembler::rsb(Register dst, Register src1, const Operand& src2, SBit s,
1568 AddrMode1(cond | RSB | s, dst, src1, src2);
1571 void Assembler::add(Register dst, Register src1, const Operand& src2, SBit s,
1573 AddrMode1(cond | ADD | s, dst, src1, src2);
1576 void Assembler::add(Register dst, Register src1, Register src2, SBit s,
1578 add(dst, src1, Operand(src2), s, cond);
1581 void Assembler::adc(Register dst, Register src1, const Operand& src2, SBit s,
1583 AddrMode1(cond | ADC | s, dst, src1, src2);
1586 void Assembler::sbc(Register dst, Register src1, const Operand& src2, SBit s,
1588 AddrMode1(cond | SBC | s, dst, src1, src2);
1591 void Assembler::rsc(Register dst, Register src1, const Operand& src2, SBit s,
1593 AddrMode1(cond | RSC | s, dst, src1, src2);
1596 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
1597 AddrMode1(cond | TST | S, no_reg, src1, src2);
1600 void Assembler::tst(Register src1, Register src2, Condition cond) {
1601 tst(src1, Operand(src2), cond);
1604 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
1605 AddrMode1(cond | TEQ | S, no_reg, src1, src2);
1608 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
1609 AddrMode1(cond | CMP | S, no_reg, src1, src2);
1612 void Assembler::cmp(Register src1, Register src2, Condition cond) {
1613 cmp(src1, Operand(src2), cond);
1622 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
1623 AddrMode1(cond | CMN | S, no_reg, src1, src2);
1626 void Assembler::orr(Register dst, Register src1, const Operand& src2, SBit s,
1628 AddrMode1(cond | ORR | s, dst, src1, src2);
1631 void Assembler::orr(Register dst, Register src1, Register src2, SBit s,
1633 orr(dst, src1, Operand(src2), s, cond);
1695 void Assembler::bic(Register dst, Register src1, const Operand& src2, SBit s,
1697 AddrMode1(cond | BIC | s, dst, src1, src2);
1704 void Assembler::asr(Register dst, Register src1, const Operand& src2, SBit s,
1706 if (src2.IsRegister()) {
1707 mov(dst, Operand(src1, ASR, src2.rm()), s, cond);
1709 mov(dst, Operand(src1, ASR, src2.immediate()), s, cond);
1713 void Assembler::lsl(Register dst, Register src1, const Operand& src2, SBit s,
1715 if (src2.IsRegister()) {
1716 mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
1718 mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
1722 void Assembler::lsr(Register dst, Register src1, const Operand& src2, SBit s,
1724 if (src2.IsRegister()) {
1725 mov(dst, Operand(src1, LSR, src2.rm()), s, cond);
1727 mov(dst, Operand(src1, LSR, src2.immediate()), s, cond);
1732 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
1734 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1735 emit(cond | A | s | dst.code() * B16 | srcA.code() * B12 | src2.code() * B8 |
1739 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
1741 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1744 src2.code() * B8 | B7 | B4 | src1.code());
1747 void Assembler::sdiv(Register dst, Register src1, Register src2,
1749 DCHECK(dst != pc && src1 != pc && src2 != pc);
1752 src2.code() * B8 | B4 | src1.code());
1755 void Assembler::udiv(Register dst, Register src1, Register src2,
1757 DCHECK(dst != pc && src1 != pc && src2 != pc);
1760 src2.code() * B8 | B4 | src1.code());
1763 void Assembler::mul(Register dst, Register src1, Register src2, SBit s,
1765 DCHECK(dst != pc && src1 != pc && src2 != pc);
1767 emit(cond | s | dst.code() * B16 | src2.code() * B8 | B7 | B4 | src1.code());
1770 void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA,
1772 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1774 srcA.code() * B12 | src2.code() * B8 | B4 | src1.code());
1777 void Assembler::smmul(Register dst, Register src1, Register src2,
1779 DCHECK(dst != pc && src1 != pc && src2 != pc);
1781 src2.code() * B8 | B4 | src1.code());
1785 Register src2, SBit s, Condition cond) {
1786 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1789 src2.code() * B8 | B7 | B4 | src1.code());
1793 Register src2, SBit s, Condition cond) {
1794 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1797 src2.code() * B8 | B7 | B4 | src1.code());
1801 Register src2, SBit s, Condition cond) {
1802 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1805 src2.code() * B8 | B7 | B4 | src1.code());
1809 Register src2, SBit s, Condition cond) {
1810 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1813 src2.code() * B8 | B7 | B4 | src1.code());
1901 void Assembler::pkhbt(Register dst, Register src1, const Operand& src2,
1908 DCHECK(src2.IsImmediateShiftedRegister());
1909 DCHECK(src2.rm() != pc);
1910 DCHECK((src2.shift_imm_ >= 0) && (src2.shift_imm_ <= 31));
1911 DCHECK(src2.shift_op() == LSL);
1913 src2.shift_imm_ * B7 | B4 | src2.rm().code());
1916 void Assembler::pkhtb(Register dst, Register src1, const Operand& src2,
1923 DCHECK(src2.IsImmediateShiftedRegister());
1924 DCHECK(src2.rm() != pc);
1925 DCHECK((src2.shift_imm_ >= 1) && (src2.shift_imm_ <= 32));
1926 DCHECK(src2.shift_op() == ASR);
1927 int asr = (src2.shift_imm_ == 32) ? 0 : src2.shift_imm_;
1929 B6 | B4 | src2.rm().code());
1943 void Assembler::sxtab(Register dst, Register src1, Register src2, int rotate,
1950 DCHECK(src2 != pc);
1953 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
1967 void Assembler::sxtah(Register dst, Register src1, Register src2, int rotate,
1974 DCHECK(src2 != pc);
1977 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
1991 void Assembler::uxtab(Register dst, Register src1, Register src2, int rotate,
1998 DCHECK(src2 != pc);
2001 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
2026 void Assembler::uxtah(Register dst, Register src1, Register src2, int rotate,
2033 DCHECK(src2 != pc);
2036 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
2131 void Assembler::strd(Register src1, Register src2, const MemOperand& dst,
2136 DCHECK_EQ(src1.code() + 1, src2.code());
2159 void Assembler::strex(Register src1, Register src2, Register dst,
2166 DCHECK(src2 != pc);
2168 DCHECK(src1 != src2);
2170 src2.code());
2182 void Assembler::strexb(Register src1, Register src2, Register dst,
2189 DCHECK(src2 != pc);
2191 DCHECK(src1 != src2);
2193 0xF9 * B4 | src2.code());
2205 void Assembler::strexh(Register src1, Register src2, Register dst,
2212 DCHECK(src2 != pc);
2214 DCHECK(src1 != src2);
2216 0xF9 * B4 | src2.code());
2231 void Assembler::strexd(Register res, Register src1, Register src2, Register dst,
2238 DCHECK_EQ(src1.code() + 1, src2.code());
2909 const Register src2, const Condition cond) {
2915 DCHECK(src1 != pc && src2 != pc);
2918 emit(cond | 0xC * B24 | B22 | src2.code() * B16 | src1.code() * B12 |
3187 const DwVfpRegister src2, const Condition cond) {
3195 DCHECK(VfpRegisterIsAvailable(src2));
3201 src2.split_code(&vm, &m);
3207 const SwVfpRegister src2, const Condition cond) {
3218 src2.split_code(&vm, &m);
3224 const DwVfpRegister src2, const Condition cond) {
3232 DCHECK(VfpRegisterIsAvailable(src2));
3238 src2.split_code(&vm, &m);
3244 const SwVfpRegister src2, const Condition cond) {
3255 src2.split_code(&vm, &m);
3261 const DwVfpRegister src2, const Condition cond) {
3269 DCHECK(VfpRegisterIsAvailable(src2));
3275 src2.split_code(&vm, &m);
3281 const SwVfpRegister src2, const Condition cond) {
3292 src2.split_code(&vm, &m);
3298 const DwVfpRegister src2, const Condition cond) {
3304 DCHECK(VfpRegisterIsAvailable(src2));
3310 src2.split_code(&vm, &m);
3316 const SwVfpRegister src2, const Condition cond) {
3325 src2.split_code(&vm, &m);
3331 const DwVfpRegister src2, const Condition cond) {
3337 DCHECK(VfpRegisterIsAvailable(src2));
3343 src2.split_code(&vm, &m);
3349 const SwVfpRegister src2, const Condition cond) {
3358 src2.split_code(&vm, &m);
3364 const DwVfpRegister src2, const Condition cond) {
3372 DCHECK(VfpRegisterIsAvailable(src2));
3378 src2.split_code(&vm, &m);
3384 const SwVfpRegister src2, const Condition cond) {
3395 src2.split_code(&vm, &m);
3400 void Assembler::vcmp(const DwVfpRegister src1, const DwVfpRegister src2,
3407 DCHECK(VfpRegisterIsAvailable(src2));
3411 src2.split_code(&vm, &m);
3416 void Assembler::vcmp(const SwVfpRegister src1, const SwVfpRegister src2,
3425 src2.split_code(&vm, &m);
3430 void Assembler::vcmp(const DwVfpRegister src1, const double src2,
3437 DCHECK_EQ(src2, 0.0);
3444 void Assembler::vcmp(const SwVfpRegister src1, const float src2,
3450 DCHECK_EQ(src2, 0.0);
3458 const DwVfpRegister src2) {
3467 src2.split_code(&vm, &m);
3474 const SwVfpRegister src2) {
3483 src2.split_code(&vm, &m);
3490 const DwVfpRegister src2) {
3499 src2.split_code(&vm, &m);
3506 const SwVfpRegister src2) {
3515 src2.split_code(&vm, &m);
3522 const DwVfpRegister src1, const DwVfpRegister src2) {
3532 src2.split_code(&vm, &m);
3554 const SwVfpRegister src1, const SwVfpRegister src2) {
3564 src2.split_code(&vm, &m);
4264 QwNeonRegister src2) {
4269 src2.code()));
4273 QwNeonRegister src2) {
4278 src2.code()));
4282 QwNeonRegister src2) {
4287 src2.code()));
4291 DwVfpRegister src2) {
4296 src2.code()));
4300 QwNeonRegister src2) {
4305 src2.code()));
4309 QwNeonRegister src2) {
4314 src2.code()));
4318 QwNeonRegister src2) {
4323 src2.code()));
4340 QwNeonRegister src1, QwNeonRegister src2) {
4381 src2.split_code(&vm, &m);
4404 QwNeonRegister src2) {
4454 src2.split_code(&vm, &m);
4462 QwNeonRegister src1, QwNeonRegister src2) {
4465 return EncodeNeonBinOp(op, static_cast<NeonDataType>(size), dst, src1, src2);
4469 QwNeonRegister src2) {
4473 emit(EncodeNeonBinOp(VADDF, dst, src1, src2));
4477 QwNeonRegister src2) {
4481 emit(EncodeNeonBinOp(VADD, size, dst, src1, src2));
4485 QwNeonRegister src2) {
4489 emit(EncodeNeonBinOp(VQADD, dt, dst, src1, src2));
4493 QwNeonRegister src2) {
4497 emit(EncodeNeonBinOp(VSUBF, dst, src1, src2));
4501 QwNeonRegister src2) {
4505 emit(EncodeNeonBinOp(VSUB, size, dst, src1, src2));
4509 QwNeonRegister src2) {
4513 emit(EncodeNeonBinOp(VQSUB, dt, dst, src1, src2));
4517 DwVfpRegister src2) {
4526 src2.split_code(&vm, &m);
4536 QwNeonRegister src2) {
4540 emit(EncodeNeonBinOp(VMULF, dst, src1, src2));
4544 QwNeonRegister src2) {
4548 emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2));
4552 DwVfpRegister src2) {
4561 src2.split_code(&vm, &m);
4569 QwNeonRegister src2) {
4573 emit(EncodeNeonBinOp(VMINF, dst, src1, src2));
4577 QwNeonRegister src2) {
4581 emit(EncodeNeonBinOp(VMIN, dt, dst, src1, src2));
4585 QwNeonRegister src2) {
4589 emit(EncodeNeonBinOp(VMAXF, dst, src1, src2));
4593 QwNeonRegister src2) {
4597 emit(EncodeNeonBinOp(VMAX, dt, dst, src1, src2));
4751 QwNeonRegister src2) {
4755 emit(EncodeNeonBinOp(VRECPS, dst, src1, src2));
4759 QwNeonRegister src2) {
4763 emit(EncodeNeonBinOp(VRSQRTS, dst, src1, src2));
4770 DwVfpRegister src2) {
4790 src2.split_code(&vm, &m);
4798 DwVfpRegister src2) {
4807 src2.split_code(&vm, &m);
4814 DwVfpRegister src2) {
4818 emit(EncodeNeonPairwiseOp(VPADD, NeonSizeToDataType(size), dst, src1, src2));
4822 DwVfpRegister src2) {
4826 emit(EncodeNeonPairwiseOp(VPMIN, dt, dst, src1, src2));
4830 DwVfpRegister src2) {
4834 emit(EncodeNeonPairwiseOp(VPMAX, dt, dst, src1, src2));
4870 QwNeonRegister src2) {
4874 emit(EncodeNeonBinOp(VTST, size, dst, src1, src2));
4878 QwNeonRegister src2) {
4882 emit(EncodeNeonBinOp(VCEQF, dst, src1, src2));
4886 QwNeonRegister src2) {
4890 emit(EncodeNeonBinOp(VCEQ, size, dst, src1, src2));
4903 QwNeonRegister src2) {
4907 emit(EncodeNeonBinOp(VCGEF, dst, src1, src2));
4911 QwNeonRegister src2) {
4915 emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2));
4919 QwNeonRegister src2) {
4923 emit(EncodeNeonBinOp(VCGTF, dst, src1, src2));
4927 QwNeonRegister src2) {
4931 emit(EncodeNeonBinOp(VCGT, dt, dst, src1, src2));
4944 QwNeonRegister src2) {
4948 emit(EncodeNeonBinOp(VRHADD, dt, dst, src1, src2));
4952 QwNeonRegister src2, int bytes) {
4961 src2.split_code(&vm, &m);
4967 void Assembler::vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4969 vtrn(size, src1, src2);
4974 emit(EncodeNeonUnaryOp(VZIP, NEON_D, size, src1.code(), src2.code()));
4978 void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4982 emit(EncodeNeonUnaryOp(VZIP, NEON_Q, size, src1.code(), src2.code()));
4985 void Assembler::vuzp(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4987 vtrn(size, src1, src2);
4992 emit(EncodeNeonUnaryOp(VUZP, NEON_D, size, src1.code(), src2.code()));
4996 void Assembler::vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
5000 emit(EncodeNeonUnaryOp(VUZP, NEON_Q, size, src1.code(), src2.code()));
5024 void Assembler::vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
5028 emit(EncodeNeonUnaryOp(VTRN, NEON_D, size, src1.code(), src2.code()));
5031 void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
5035 emit(EncodeNeonUnaryOp(VTRN, NEON_Q, size, src1.code(), src2.code()));
5055 QwNeonRegister src1, QwNeonRegister src2) {
5058 emit(EncodeNeonBinOp(VQRDMULH, dt, dst, src1, src2));