Lines Matching defs:src1
1536 void Assembler::and_(Register dst, Register src1, const Operand& src2, SBit s,
1538 AddrMode1(cond | AND | s, dst, src1, src2);
1541 void Assembler::and_(Register dst, Register src1, Register src2, SBit s,
1543 and_(dst, src1, Operand(src2), s, cond);
1546 void Assembler::eor(Register dst, Register src1, const Operand& src2, SBit s,
1548 AddrMode1(cond | EOR | s, dst, src1, src2);
1551 void Assembler::eor(Register dst, Register src1, Register src2, SBit s,
1553 AddrMode1(cond | EOR | s, dst, src1, Operand(src2));
1556 void Assembler::sub(Register dst, Register src1, const Operand& src2, SBit s,
1558 AddrMode1(cond | SUB | s, dst, src1, src2);
1561 void Assembler::sub(Register dst, Register src1, Register src2, SBit s,
1563 sub(dst, src1, Operand(src2), s, cond);
1566 void Assembler::rsb(Register dst, Register src1, const Operand& src2, SBit s,
1568 AddrMode1(cond | RSB | s, dst, src1, src2);
1571 void Assembler::add(Register dst, Register src1, const Operand& src2, SBit s,
1573 AddrMode1(cond | ADD | s, dst, src1, src2);
1576 void Assembler::add(Register dst, Register src1, Register src2, SBit s,
1578 add(dst, src1, Operand(src2), s, cond);
1581 void Assembler::adc(Register dst, Register src1, const Operand& src2, SBit s,
1583 AddrMode1(cond | ADC | s, dst, src1, src2);
1586 void Assembler::sbc(Register dst, Register src1, const Operand& src2, SBit s,
1588 AddrMode1(cond | SBC | s, dst, src1, src2);
1591 void Assembler::rsc(Register dst, Register src1, const Operand& src2, SBit s,
1593 AddrMode1(cond | RSC | s, dst, src1, src2);
1596 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
1597 AddrMode1(cond | TST | S, no_reg, src1, src2);
1600 void Assembler::tst(Register src1, Register src2, Condition cond) {
1601 tst(src1, Operand(src2), cond);
1604 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
1605 AddrMode1(cond | TEQ | S, no_reg, src1, src2);
1608 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
1609 AddrMode1(cond | CMP | S, no_reg, src1, src2);
1612 void Assembler::cmp(Register src1, Register src2, Condition cond) {
1613 cmp(src1, Operand(src2), cond);
1622 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
1623 AddrMode1(cond | CMN | S, no_reg, src1, src2);
1626 void Assembler::orr(Register dst, Register src1, const Operand& src2, SBit s,
1628 AddrMode1(cond | ORR | s, dst, src1, src2);
1631 void Assembler::orr(Register dst, Register src1, Register src2, SBit s,
1633 orr(dst, src1, Operand(src2), s, cond);
1695 void Assembler::bic(Register dst, Register src1, const Operand& src2, SBit s,
1697 AddrMode1(cond | BIC | s, dst, src1, src2);
1704 void Assembler::asr(Register dst, Register src1, const Operand& src2, SBit s,
1707 mov(dst, Operand(src1, ASR, src2.rm()), s, cond);
1709 mov(dst, Operand(src1, ASR, src2.immediate()), s, cond);
1713 void Assembler::lsl(Register dst, Register src1, const Operand& src2, SBit s,
1716 mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
1718 mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
1722 void Assembler::lsr(Register dst, Register src1, const Operand& src2, SBit s,
1725 mov(dst, Operand(src1, LSR, src2.rm()), s, cond);
1727 mov(dst, Operand(src1, LSR, src2.immediate()), s, cond);
1732 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
1734 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1736 B7 | B4 | src1.code());
1739 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
1741 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1744 src2.code() * B8 | B7 | B4 | src1.code());
1747 void Assembler::sdiv(Register dst, Register src1, Register src2,
1749 DCHECK(dst != pc && src1 != pc && src2 != pc);
1752 src2.code() * B8 | B4 | src1.code());
1755 void Assembler::udiv(Register dst, Register src1, Register src2,
1757 DCHECK(dst != pc && src1 != pc && src2 != pc);
1760 src2.code() * B8 | B4 | src1.code());
1763 void Assembler::mul(Register dst, Register src1, Register src2, SBit s,
1765 DCHECK(dst != pc && src1 != pc && src2 != pc);
1767 emit(cond | s | dst.code() * B16 | src2.code() * B8 | B7 | B4 | src1.code());
1770 void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA,
1772 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1774 srcA.code() * B12 | src2.code() * B8 | B4 | src1.code());
1777 void Assembler::smmul(Register dst, Register src1, Register src2,
1779 DCHECK(dst != pc && src1 != pc && src2 != pc);
1781 src2.code() * B8 | B4 | src1.code());
1784 void Assembler::smlal(Register dstL, Register dstH, Register src1,
1786 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1789 src2.code() * B8 | B7 | B4 | src1.code());
1792 void Assembler::smull(Register dstL, Register dstH, Register src1,
1794 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1797 src2.code() * B8 | B7 | B4 | src1.code());
1800 void Assembler::umlal(Register dstL, Register dstH, Register src1,
1802 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1805 src2.code() * B8 | B7 | B4 | src1.code());
1808 void Assembler::umull(Register dstL, Register dstH, Register src1,
1810 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1813 src2.code() * B8 | B7 | B4 | src1.code());
1901 void Assembler::pkhbt(Register dst, Register src1, const Operand& src2,
1907 DCHECK(src1 != pc);
1912 emit(cond | 0x68 * B20 | src1.code() * B16 | dst.code() * B12 |
1916 void Assembler::pkhtb(Register dst, Register src1, const Operand& src2,
1922 DCHECK(src1 != pc);
1928 emit(cond | 0x68 * B20 | src1.code() * B16 | dst.code() * B12 | asr * B7 |
1943 void Assembler::sxtab(Register dst, Register src1, Register src2, int rotate,
1949 DCHECK(src1 != pc);
1952 emit(cond | 0x6A * B20 | src1.code() * B16 | dst.code() * B12 |
1967 void Assembler::sxtah(Register dst, Register src1, Register src2, int rotate,
1973 DCHECK(src1 != pc);
1976 emit(cond | 0x6B * B20 | src1.code() * B16 | dst.code() * B12 |
1991 void Assembler::uxtab(Register dst, Register src1, Register src2, int rotate,
1997 DCHECK(src1 != pc);
2000 emit(cond | 0x6E * B20 | src1.code() * B16 | dst.code() * B12 |
2026 void Assembler::uxtah(Register dst, Register src1, Register src2, int rotate,
2032 DCHECK(src1 != pc);
2035 emit(cond | 0x6F * B20 | src1.code() * B16 | dst.code() * B12 |
2131 void Assembler::strd(Register src1, Register src2, const MemOperand& dst,
2134 DCHECK(src1 != lr); // r14.
2135 DCHECK_EQ(0, src1.code() % 2);
2136 DCHECK_EQ(src1.code() + 1, src2.code());
2137 AddrMode3(cond | B7 | B6 | B5 | B4, src1, dst);
2159 void Assembler::strex(Register src1, Register src2, Register dst,
2165 DCHECK(src1 != pc);
2167 DCHECK(src1 != dst);
2168 DCHECK(src1 != src2);
2169 emit(cond | B24 | B23 | dst.code() * B16 | src1.code() * B12 | 0xF9 * B4 |
2182 void Assembler::strexb(Register src1, Register src2, Register dst,
2188 DCHECK(src1 != pc);
2190 DCHECK(src1 != dst);
2191 DCHECK(src1 != src2);
2192 emit(cond | B24 | B23 | B22 | dst.code() * B16 | src1.code() * B12 |
2205 void Assembler::strexh(Register src1, Register src2, Register dst,
2211 DCHECK(src1 != pc);
2213 DCHECK(src1 != dst);
2214 DCHECK(src1 != src2);
2215 emit(cond | B24 | B23 | B22 | B21 | dst.code() * B16 | src1.code() * B12 |
2231 void Assembler::strexd(Register res, Register src1, Register src2, Register dst,
2234 DCHECK(src1 != lr); // r14.
2237 DCHECK_EQ(0, src1.code() % 2);
2238 DCHECK_EQ(src1.code() + 1, src2.code());
2240 0xF9 * B4 | src1.code());
2908 void Assembler::vmov(const DwVfpRegister dst, const Register src1,
2915 DCHECK(src1 != pc && src2 != pc);
2918 emit(cond | 0xC * B24 | B22 | src2.code() * B16 | src1.code() * B12 |
3186 void Assembler::vadd(const DwVfpRegister dst, const DwVfpRegister src1,
3194 DCHECK(VfpRegisterIsAvailable(src1));
3199 src1.split_code(&vn, &n);
3206 void Assembler::vadd(const SwVfpRegister dst, const SwVfpRegister src1,
3216 src1.split_code(&vn, &n);
3223 void Assembler::vsub(const DwVfpRegister dst, const DwVfpRegister src1,
3231 DCHECK(VfpRegisterIsAvailable(src1));
3236 src1.split_code(&vn, &n);
3243 void Assembler::vsub(const SwVfpRegister dst, const SwVfpRegister src1,
3253 src1.split_code(&vn, &n);
3260 void Assembler::vmul(const DwVfpRegister dst, const DwVfpRegister src1,
3268 DCHECK(VfpRegisterIsAvailable(src1));
3273 src1.split_code(&vn, &n);
3280 void Assembler::vmul(const SwVfpRegister dst, const SwVfpRegister src1,
3290 src1.split_code(&vn, &n);
3297 void Assembler::vmla(const DwVfpRegister dst, const DwVfpRegister src1,
3303 DCHECK(VfpRegisterIsAvailable(src1));
3308 src1.split_code(&vn, &n);
3315 void Assembler::vmla(const SwVfpRegister dst, const SwVfpRegister src1,
3323 src1.split_code(&vn, &n);
3330 void Assembler::vmls(const DwVfpRegister dst, const DwVfpRegister src1,
3336 DCHECK(VfpRegisterIsAvailable(src1));
3341 src1.split_code(&vn, &n);
3348 void Assembler::vmls(const SwVfpRegister dst, const SwVfpRegister src1,
3356 src1.split_code(&vn, &n);
3363 void Assembler::vdiv(const DwVfpRegister dst, const DwVfpRegister src1,
3371 DCHECK(VfpRegisterIsAvailable(src1));
3376 src1.split_code(&vn, &n);
3383 void Assembler::vdiv(const SwVfpRegister dst, const SwVfpRegister src1,
3393 src1.split_code(&vn, &n);
3400 void Assembler::vcmp(const DwVfpRegister src1, const DwVfpRegister src2,
3406 DCHECK(VfpRegisterIsAvailable(src1));
3409 src1.split_code(&vd, &d);
3416 void Assembler::vcmp(const SwVfpRegister src1, const SwVfpRegister src2,
3423 src1.split_code(&vd, &d);
3430 void Assembler::vcmp(const DwVfpRegister src1, const double src2,
3436 DCHECK(VfpRegisterIsAvailable(src1));
3439 src1.split_code(&vd, &d);
3444 void Assembler::vcmp(const SwVfpRegister src1, const float src2,
3452 src1.split_code(&vd, &d);
3457 void Assembler::vmaxnm(const DwVfpRegister dst, const DwVfpRegister src1,
3465 src1.split_code(&vn, &n);
3473 void Assembler::vmaxnm(const SwVfpRegister dst, const SwVfpRegister src1,
3481 src1.split_code(&vn, &n);
3489 void Assembler::vminnm(const DwVfpRegister dst, const DwVfpRegister src1,
3497 src1.split_code(&vn, &n);
3505 void Assembler::vminnm(const SwVfpRegister dst, const SwVfpRegister src1,
3513 src1.split_code(&vn, &n);
3522 const DwVfpRegister src1, const DwVfpRegister src2) {
3530 src1.split_code(&vn, &n);
3554 const SwVfpRegister src1, const SwVfpRegister src2) {
3562 src1.split_code(&vn, &n);
4263 void Assembler::vand(QwNeonRegister dst, QwNeonRegister src1,
4268 emit(EncodeNeonBinaryBitwiseOp(VAND, NEON_Q, dst.code(), src1.code(),
4272 void Assembler::vbic(QwNeonRegister dst, QwNeonRegister src1,
4277 emit(EncodeNeonBinaryBitwiseOp(VBIC, NEON_Q, dst.code(), src1.code(),
4281 void Assembler::vbsl(QwNeonRegister dst, QwNeonRegister src1,
4286 emit(EncodeNeonBinaryBitwiseOp(VBSL, NEON_Q, dst.code(), src1.code(),
4290 void Assembler::veor(DwVfpRegister dst, DwVfpRegister src1,
4295 emit(EncodeNeonBinaryBitwiseOp(VEOR, NEON_D, dst.code(), src1.code(),
4299 void Assembler::veor(QwNeonRegister dst, QwNeonRegister src1,
4304 emit(EncodeNeonBinaryBitwiseOp(VEOR, NEON_Q, dst.code(), src1.code(),
4308 void Assembler::vorr(QwNeonRegister dst, QwNeonRegister src1,
4313 emit(EncodeNeonBinaryBitwiseOp(VORR, NEON_Q, dst.code(), src1.code(),
4317 void Assembler::vorn(QwNeonRegister dst, QwNeonRegister src1,
4322 emit(EncodeNeonBinaryBitwiseOp(VORN, NEON_Q, dst.code(), src1.code(),
4340 QwNeonRegister src1, QwNeonRegister src2) {
4379 src1.split_code(&vn, &n);
4403 QwNeonRegister dst, QwNeonRegister src1,
4452 src1.split_code(&vn, &n);
4462 QwNeonRegister src1, QwNeonRegister src2) {
4465 return EncodeNeonBinOp(op, static_cast<NeonDataType>(size), dst, src1, src2);
4468 void Assembler::vadd(QwNeonRegister dst, QwNeonRegister src1,
4473 emit(EncodeNeonBinOp(VADDF, dst, src1, src2));
4476 void Assembler::vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4481 emit(EncodeNeonBinOp(VADD, size, dst, src1, src2));
4484 void Assembler::vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4489 emit(EncodeNeonBinOp(VQADD, dt, dst, src1, src2));
4492 void Assembler::vsub(QwNeonRegister dst, QwNeonRegister src1,
4497 emit(EncodeNeonBinOp(VSUBF, dst, src1, src2));
4500 void Assembler::vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4505 emit(EncodeNeonBinOp(VSUB, size, dst, src1, src2));
4508 void Assembler::vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4513 emit(EncodeNeonBinOp(VQSUB, dt, dst, src1, src2));
4516 void Assembler::vmlal(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
4524 src1.split_code(&vn, &n);
4535 void Assembler::vmul(QwNeonRegister dst, QwNeonRegister src1,
4540 emit(EncodeNeonBinOp(VMULF, dst, src1, src2));
4543 void Assembler::vmul(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4548 emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2));
4551 void Assembler::vmull(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
4559 src1.split_code(&vn, &n);
4568 void Assembler::vmin(QwNeonRegister dst, QwNeonRegister src1,
4573 emit(EncodeNeonBinOp(VMINF, dst, src1, src2));
4576 void Assembler::vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4581 emit(EncodeNeonBinOp(VMIN, dt, dst, src1, src2));
4584 void Assembler::vmax(QwNeonRegister dst, QwNeonRegister src1,
4589 emit(EncodeNeonBinOp(VMAXF, dst, src1, src2));
4592 void Assembler::vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4597 emit(EncodeNeonBinOp(VMAX, dt, dst, src1, src2));
4750 void Assembler::vrecps(QwNeonRegister dst, QwNeonRegister src1,
4755 emit(EncodeNeonBinOp(VRECPS, dst, src1, src2));
4758 void Assembler::vrsqrts(QwNeonRegister dst, QwNeonRegister src1,
4763 emit(EncodeNeonBinOp(VRSQRTS, dst, src1, src2));
4769 DwVfpRegister dst, DwVfpRegister src1,
4788 src1.split_code(&vn, &n);
4797 void Assembler::vpadd(DwVfpRegister dst, DwVfpRegister src1,
4805 src1.split_code(&vn, &n);
4813 void Assembler::vpadd(NeonSize size, DwVfpRegister dst, DwVfpRegister src1,
4818 emit(EncodeNeonPairwiseOp(VPADD, NeonSizeToDataType(size), dst, src1, src2));
4821 void Assembler::vpmin(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1,
4826 emit(EncodeNeonPairwiseOp(VPMIN, dt, dst, src1, src2));
4829 void Assembler::vpmax(NeonDataType dt, DwVfpRegister dst, DwVfpRegister src1,
4834 emit(EncodeNeonPairwiseOp(VPMAX, dt, dst, src1, src2));
4869 void Assembler::vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4874 emit(EncodeNeonBinOp(VTST, size, dst, src1, src2));
4877 void Assembler::vceq(QwNeonRegister dst, QwNeonRegister src1,
4882 emit(EncodeNeonBinOp(VCEQF, dst, src1, src2));
4885 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4890 emit(EncodeNeonBinOp(VCEQ, size, dst, src1, src2));
4893 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
4899 emit(EncodeNeonUnaryOp(VCEQ0, NEON_Q, size, dst.code(), src1.code()));
4902 void Assembler::vcge(QwNeonRegister dst, QwNeonRegister src1,
4907 emit(EncodeNeonBinOp(VCGEF, dst, src1, src2));
4910 void Assembler::vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4915 emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2));
4918 void Assembler::vcgt(QwNeonRegister dst, QwNeonRegister src1,
4923 emit(EncodeNeonBinOp(VCGTF, dst, src1, src2));
4926 void Assembler::vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4931 emit(EncodeNeonBinOp(VCGT, dt, dst, src1, src2));
4943 void Assembler::vrhadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
4948 emit(EncodeNeonBinOp(VRHADD, dt, dst, src1, src2));
4951 void Assembler::vext(QwNeonRegister dst, QwNeonRegister src1,
4959 src1.split_code(&vn, &n);
4967 void Assembler::vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4969 vtrn(size, src1, src2);
4974 emit(EncodeNeonUnaryOp(VZIP, NEON_D, size, src1.code(), src2.code()));
4978 void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4982 emit(EncodeNeonUnaryOp(VZIP, NEON_Q, size, src1.code(), src2.code()));
4985 void Assembler::vuzp(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4987 vtrn(size, src1, src2);
4992 emit(EncodeNeonUnaryOp(VUZP, NEON_D, size, src1.code(), src2.code()));
4996 void Assembler::vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
5000 emit(EncodeNeonUnaryOp(VUZP, NEON_Q, size, src1.code(), src2.code()));
5024 void Assembler::vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
5028 emit(EncodeNeonUnaryOp(VTRN, NEON_D, size, src1.code(), src2.code()));
5031 void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
5035 emit(EncodeNeonUnaryOp(VTRN, NEON_Q, size, src1.code(), src2.code()));
5055 QwNeonRegister src1, QwNeonRegister src2) {
5058 emit(EncodeNeonBinOp(VQRDMULH, dt, dst, src1, src2));