Lines Matching defs:shift
1054 // For 0x000FF000, count trailing zeros and shift down to 0x000000FF. Note
4622 int shift) {
4627 DCHECK(shift >= 0 && size_in_bits > shift);
4628 imm6 = size_in_bits + shift;
4633 DCHECK(shift > 0 && size_in_bits >= shift);
4634 imm6 = 2 * size_in_bits - shift;
4639 DCHECK(shift >= 0 && size_in_bits > shift);
4640 imm6 = size_in_bits + shift;
4645 DCHECK(shift > 0 && size_in_bits >= shift);
4646 imm6 = 2 * size_in_bits - shift;
4651 DCHECK(shift > 0 && size_in_bits >= shift);
4652 imm6 = 2 * size_in_bits - shift;
4674 int shift) {
4676 // Qd = vshl(Qm, bits) SIMD shift left immediate.
4679 dst.code(), src.code(), shift));
4683 QwNeonRegister shift) {
4685 // Qd = vshl(Qm, Qn) SIMD shift left Register.
4688 shift.code()));
4692 int shift) {
4694 // Dd = vshr(Dm, bits) SIMD shift right immediate.
4697 dst.code(), src.code(), shift));
4701 int shift) {
4703 // Qd = vshr(Qm, bits) SIMD shift right immediate.
4706 dst.code(), src.code(), shift));
4710 int shift) {
4712 // Dd = vsli(Dm, bits) SIMD shift left and insert.
4715 shift));
4719 int shift) {
4721 // Dd = vsri(Dm, bits) SIMD shift right and insert.
4724 shift));
4730 // Dd = vsra(Dm, imm) SIMD shift right and accumulate.