Lines Matching defs:rotate
1069 // For 0xF000000F, rotate by 16 to get 0x000FF000 and continue as if it
1932 void Assembler::sxtb(Register dst, Register src, int rotate, Condition cond) {
1935 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1938 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
1940 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
1943 void Assembler::sxtab(Register dst, Register src1, Register src2, int rotate,
1947 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1951 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
1953 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
1956 void Assembler::sxth(Register dst, Register src, int rotate, Condition cond) {
1959 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1962 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
1964 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
1967 void Assembler::sxtah(Register dst, Register src1, Register src2, int rotate,
1971 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1975 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
1977 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
1980 void Assembler::uxtb(Register dst, Register src, int rotate, Condition cond) {
1983 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1986 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
1988 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
1991 void Assembler::uxtab(Register dst, Register src1, Register src2, int rotate,
1995 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
1999 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
2001 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
2004 void Assembler::uxtb16(Register dst, Register src, int rotate, Condition cond) {
2007 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
2010 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
2012 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
2015 void Assembler::uxth(Register dst, Register src, int rotate, Condition cond) {
2018 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
2021 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
2023 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src.code());
2026 void Assembler::uxtah(Register dst, Register src1, Register src2, int rotate,
2030 // Rd(15-12) | rotate(11-10) | 00(9-8)| 0111(7-4) | Rm(3-0)
2034 DCHECK(rotate == 0 || rotate == 8 || rotate == 16 || rotate == 24);
2036 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
5140 int rotate = Instruction::RotateValue(instr) * 2;
5142 return base::bits::RotateRight32(immed8, rotate);