Lines Matching defs:cond
733 // ldr<cond> <Rd>, [pc +/- offset_12].
743 // vldr<cond> <Dd>, [pc +/- offset_10].
922 Condition cond = Instruction::ConditionField(instr);
925 if (cond == kSpecialCondition) {
934 switch (cond) {
1192 Condition cond) {
1203 movw(target, imm32 & 0xFFFF, cond);
1204 movt(target, imm32 >> 16, cond);
1206 mov(rd, target, LeaveCC, cond);
1217 ldr_pcrel(rd, 0, cond);
1244 Condition cond = Instruction::ConditionField(instr);
1249 Move32BitImmediate(rd, x, cond);
1266 add(rd, rd, Operand(imm & mask), LeaveCC, cond);
1269 add(rd, rd, Operand(imm), LeaveCC, cond);
1278 mov(scratch, x, LeaveCC, cond);
1462 void Assembler::b(int branch_offset, Condition cond, RelocInfo::Mode rmode) {
1473 emit(cond | B27 | B25 | (imm24 & kImm24Mask));
1475 if (cond == al) {
1481 void Assembler::bl(int branch_offset, Condition cond, RelocInfo::Mode rmode) {
1492 emit(cond | B27 | B25 | B24 | (imm24 & kImm24Mask));
1509 void Assembler::blx(Register target, Condition cond) {
1511 emit(cond | B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BLX | target.code());
1514 void Assembler::bx(Register target, Condition cond) {
1516 emit(cond | B24 | B21 | 15 * B16 | 15 * B12 | 15 * B8 | BX | target.code());
1519 void Assembler::b(Label* L, Condition cond) {
1521 b(branch_offset(L), cond);
1524 void Assembler::bl(Label* L, Condition cond) {
1526 bl(branch_offset(L), cond);
1537 Condition cond) {
1538 AddrMode1(cond | AND | s, dst, src1, src2);
1542 Condition cond) {
1543 and_(dst, src1, Operand(src2), s, cond);
1547 Condition cond) {
1548 AddrMode1(cond | EOR | s, dst, src1, src2);
1552 Condition cond) {
1553 AddrMode1(cond | EOR | s, dst, src1, Operand(src2));
1557 Condition cond) {
1558 AddrMode1(cond | SUB | s, dst, src1, src2);
1562 Condition cond) {
1563 sub(dst, src1, Operand(src2), s, cond);
1567 Condition cond) {
1568 AddrMode1(cond | RSB | s, dst, src1, src2);
1572 Condition cond) {
1573 AddrMode1(cond | ADD | s, dst, src1, src2);
1577 Condition cond) {
1578 add(dst, src1, Operand(src2), s, cond);
1582 Condition cond) {
1583 AddrMode1(cond | ADC | s, dst, src1, src2);
1587 Condition cond) {
1588 AddrMode1(cond | SBC | s, dst, src1, src2);
1592 Condition cond) {
1593 AddrMode1(cond | RSC | s, dst, src1, src2);
1596 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
1597 AddrMode1(cond | TST | S, no_reg, src1, src2);
1600 void Assembler::tst(Register src1, Register src2, Condition cond) {
1601 tst(src1, Operand(src2), cond);
1604 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
1605 AddrMode1(cond | TEQ | S, no_reg, src1, src2);
1608 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
1609 AddrMode1(cond | CMP | S, no_reg, src1, src2);
1612 void Assembler::cmp(Register src1, Register src2, Condition cond) {
1613 cmp(src1, Operand(src2), cond);
1617 Condition cond) {
1619 emit(cond | I | CMP | S | src.code() << 16 | raw_immediate);
1622 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
1623 AddrMode1(cond | CMN | S, no_reg, src1, src2);
1627 Condition cond) {
1628 AddrMode1(cond | ORR | s, dst, src1, src2);
1632 Condition cond) {
1633 orr(dst, src1, Operand(src2), s, cond);
1636 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
1639 DCHECK(!(src.IsRegister() && src.rm() == dst && s == LeaveCC && cond == al));
1640 AddrMode1(cond | MOV | s, dst, no_reg, src);
1643 void Assembler::mov(Register dst, Register src, SBit s, Condition cond) {
1644 mov(dst, Operand(src), s, cond);
1685 void Assembler::movw(Register reg, uint32_t immediate, Condition cond) {
1687 emit(cond | 0x30 * B20 | reg.code() * B12 | EncodeMovwImmediate(immediate));
1690 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) {
1692 emit(cond | 0x34 * B20 | reg.code() * B12 | EncodeMovwImmediate(immediate));
1696 Condition cond) {
1697 AddrMode1(cond | BIC | s, dst, src1, src2);
1700 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
1701 AddrMode1(cond | MVN | s, dst, no_reg, src);
1705 Condition cond) {
1707 mov(dst, Operand(src1, ASR, src2.rm()), s, cond);
1709 mov(dst, Operand(src1, ASR, src2.immediate()), s, cond);
1714 Condition cond) {
1716 mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
1718 mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
1723 Condition cond) {
1725 mov(dst, Operand(src1, LSR, src2.rm()), s, cond);
1727 mov(dst, Operand(src1, LSR, src2.immediate()), s, cond);
1733 SBit s, Condition cond) {
1735 emit(cond | A | s | dst.code() * B16 | srcA.code() * B12 | src2.code() * B8 |
1740 Condition cond) {
1743 emit(cond | B22 | B21 | dst.code() * B16 | srcA.code() * B12 |
1748 Condition cond) {
1751 emit(cond | B26 | B25 | B24 | B20 | dst.code() * B16 | 0xF * B12 |
1756 Condition cond) {
1759 emit(cond | B26 | B25 | B24 | B21 | B20 | dst.code() * B16 | 0xF * B12 |
1764 Condition cond) {
1767 emit(cond | s | dst.code() * B16 | src2.code() * B8 | B7 | B4 | src1.code());
1771 Condition cond) {
1773 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 |
1778 Condition cond) {
1780 emit(cond | B26 | B25 | B24 | B22 | B20 | dst.code() * B16 | 0xF * B12 |
1785 Register src2, SBit s, Condition cond) {
1788 emit(cond | B23 | B22 | A | s | dstH.code() * B16 | dstL.code() * B12 |
1793 Register src2, SBit s, Condition cond) {
1796 emit(cond | B23 | B22 | s | dstH.code() * B16 | dstL.code() * B12 |
1801 Register src2, SBit s, Condition cond) {
1804 emit(cond | B23 | A | s | dstH.code() * B16 | dstL.code() * B12 |
1809 Register src2, SBit s, Condition cond) {
1812 emit(cond | B23 | s | dstH.code() * B16 | dstL.code() * B12 |
1817 void Assembler::clz(Register dst, Register src, Condition cond) {
1819 emit(cond | B24 | B22 | B21 | 15 * B16 | dst.code() * B12 | 15 * B8 | CLZ |
1827 Condition cond) {
1838 emit(cond | 0x6 * B24 | 0xE * B20 | satpos * B16 | dst.code() * B12 |
1849 Condition cond) {
1854 emit(cond | 0xF * B23 | B22 | B21 | (width - 1) * B16 | dst.code() * B12 |
1864 Condition cond) {
1869 emit(cond | 0xF * B23 | B21 | (width - 1) * B16 | dst.code() * B12 |
1877 void Assembler::bfc(Register dst, int lsb, int width, Condition cond) {
1883 emit(cond | 0x1F * B22 | msb * B16 | dst.code() * B12 | lsb * B7 | B4 | 0xF);
1891 Condition cond) {
1897 emit(cond | 0x1F * B22 | msb * B16 | dst.code() * B12 | lsb * B7 | B4 |
1902 Condition cond) {
1904 // cond(31-28) | 01101000(27-20) | Rn(19-16) |
1912 emit(cond | 0x68 * B20 | src1.code() * B16 | dst.code() * B12 |
1917 Condition cond) {
1919 // cond(31-28) | 01101000(27-20) | Rn(19-16) |
1928 emit(cond | 0x68 * B20 | src1.code() * B16 | dst.code() * B12 | asr * B7 |
1932 void Assembler::sxtb(Register dst, Register src, int rotate, Condition cond) {
1934 // cond(31-28) | 01101010(27-20) | 1111(19-16) |
1939 emit(cond | 0x6A * B20 | 0xF * B16 | dst.code() * B12 |
1944 Condition cond) {
1946 // cond(31-28) | 01101010(27-20) | Rn(19-16) |
1952 emit(cond | 0x6A * B20 | src1.code() * B16 | dst.code() * B12 |
1956 void Assembler::sxth(Register dst, Register src, int rotate, Condition cond) {
1958 // cond(31-28) | 01101011(27-20) | 1111(19-16) |
1963 emit(cond | 0x6B * B20 | 0xF * B16 | dst.code() * B12 |
1968 Condition cond) {
1970 // cond(31-28) | 01101011(27-20) | Rn(19-16) |
1976 emit(cond | 0x6B * B20 | src1.code() * B16 | dst.code() * B12 |
1980 void Assembler::uxtb(Register dst, Register src, int rotate, Condition cond) {
1982 // cond(31-28) | 01101110(27-20) | 1111(19-16) |
1987 emit(cond | 0x6E * B20 | 0xF * B16 | dst.code() * B12 |
1992 Condition cond) {
1994 // cond(31-28) | 01101110(27-20) | Rn(19-16) |
2000 emit(cond | 0x6E * B20 | src1.code() * B16 | dst.code() * B12 |
2004 void Assembler::uxtb16(Register dst, Register src, int rotate, Condition cond) {
2006 // cond(31-28) | 01101100(27-20) | 1111(19-16) |
2011 emit(cond | 0x6C * B20 | 0xF * B16 | dst.code() * B12 |
2015 void Assembler::uxth(Register dst, Register src, int rotate, Condition cond) {
2017 // cond(31-28) | 01101111(27-20) | 1111(19-16) |
2022 emit(cond | 0x6F * B20 | 0xF * B16 | dst.code() * B12 |
2027 Condition cond) {
2029 // cond(31-28) | 01101111(27-20) | Rn(19-16) |
2035 emit(cond | 0x6F * B20 | src1.code() * B16 | dst.code() * B12 |
2039 void Assembler::rbit(Register dst, Register src, Condition cond) {
2041 // cond(31-28) | 011011111111(27-16) | Rd(15-12) | 11110011(11-4) | Rm(3-0)
2045 emit(cond | 0x6FF * B16 | dst.code() * B12 | 0xF3 * B4 | src.code());
2048 void Assembler::rev(Register dst, Register src, Condition cond) {
2050 // cond(31-28) | 011010111111(27-16) | Rd(15-12) | 11110011(11-4) | Rm(3-0)
2053 emit(cond | 0x6BF * B16 | dst.code() * B12 | 0xF3 * B4 | src.code());
2057 void Assembler::mrs(Register dst, SRegister s, Condition cond) {
2059 emit(cond | B24 | s | 15 * B16 | dst.code() * B12);
2063 Condition cond) {
2078 msr(fields, Operand(scratch), cond);
2086 emit(cond | instr | B24 | B21 | fields | 15 * B12);
2090 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
2091 AddrMode2(cond | B26 | L, dst, src);
2094 void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
2095 AddrMode2(cond | B26, src, dst);
2098 void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
2099 AddrMode2(cond | B26 | B | L, dst, src);
2102 void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
2103 AddrMode2(cond | B26 | B, src, dst);
2106 void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
2107 AddrMode3(cond | L | B7 | H | B4, dst, src);
2110 void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
2111 AddrMode3(cond | B7 | H | B4, src, dst);
2114 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
2115 AddrMode3(cond | L | B7 | S6 | B4, dst, src);
2118 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
2119 AddrMode3(cond | L | B7 | S6 | H | B4, dst, src);
2123 Condition cond) {
2128 AddrMode3(cond | B7 | B6 | B4, dst1, src);
2132 Condition cond) {
2137 AddrMode3(cond | B7 | B6 | B5 | B4, src1, dst);
2140 void Assembler::ldr_pcrel(Register dst, int imm12, Condition cond) {
2147 emit(cond | B26 | am | L | pc.code() * B16 | dst.code() * B12 | imm12);
2151 void Assembler::ldrex(Register dst, Register src, Condition cond) {
2153 // cond(31-28) | 00011001(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0)
2156 emit(cond | B24 | B23 | B20 | src.code() * B16 | dst.code() * B12 | 0xF9F);
2160 Condition cond) {
2162 // cond(31-28) | 00011000(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) |
2169 emit(cond | B24 | B23 | dst.code() * B16 | src1.code() * B12 | 0xF9 * B4 |
2173 void Assembler::ldrexb(Register dst, Register src, Condition cond) {
2175 // cond(31-28) | 00011101(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0)
2178 emit(cond | B24 | B23 | B22 | B20 | src.code() * B16 | dst.code() * B12 |
2183 Condition cond) {
2185 // cond(31-28) | 00011100(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) |
2192 emit(cond | B24 | B23 | B22 | dst.code() * B16 | src1.code() * B12 |
2196 void Assembler::ldrexh(Register dst, Register src, Condition cond) {
2198 // cond(31-28) | 00011111(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0)
2201 emit(cond | B24 | B23 | B22 | B21 | B20 | src.code() * B16 |
2206 Condition cond) {
2208 // cond(31-28) | 00011110(27-20) | Rn(19-16) | Rd(15-12) | 11111001(11-4) |
2215 emit(cond | B24 | B23 | B22 | B21 | dst.code() * B16 | src1.code() * B12 |
2220 Condition cond) {
2221 // cond(31-28) | 00011011(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0)
2227 emit(cond | B24 | B23 | B21 | B20 | src.code() * B16 | dst1.code() * B12 |
2232 Condition cond) {
2233 // cond(31-28) | 00011010(27-20) | Rn(19-16) | Rt(15-12) | 111110011111(11-0)
2239 emit(cond | B24 | B23 | B21 | dst.code() * B16 | res.code() * B12 |
2263 Condition cond) {
2267 AddrMode4(cond | B27 | am | L, base, dst);
2270 if (cond == al && dst.has(pc)) {
2281 Condition cond) {
2282 AddrMode4(cond | B27 | am, base, src);
2288 void Assembler::stop(Condition cond, int32_t code) {
2294 svc(kStopCode + code, cond);
2296 svc(kStopCode + kMaxStopCode, cond);
2300 if (cond != al) {
2302 b(&skip, NegateCondition(cond));
2316 void Assembler::svc(uint32_t imm24, Condition cond) {
2318 emit(cond | 15 * B24 | imm24);
2363 Condition cond) {
2365 emit(cond | B27 | B26 | B25 | (opcode_1 & 15) * B20 | crn.code() * B16 |
2376 Condition cond) {
2378 emit(cond | B27 | B26 | B25 | (opcode_1 & 7) * B21 | crn.code() * B16 |
2389 Condition cond) {
2391 emit(cond | B27 | B26 | B25 | (opcode_1 & 7) * B21 | L | crn.code() * B16 |
2401 LFlag l, Condition cond) {
2402 AddrMode5(cond | B27 | B26 | l | L | coproc * B8, crd, src);
2406 LFlag l, Condition cond) {
2409 emit(cond | B27 | B26 | U | l | L | rn.code() * B16 | crd.code() * B12 |
2426 const Condition cond) {
2429 // cond(31-28) | 1101(27-24)| U(23) | D(22) | 01(21-20) | Rbase(19-16) |
2443 emit(cond | 0xD * B24 | u * B23 | d * B22 | B20 | base.code() * B16 |
2456 emit(cond | 0xD * B24 | d * B22 | B20 | scratch.code() * B16 | vd * B12 |
2462 const Condition cond) {
2470 vldr(dst, scratch, 0, cond);
2472 vldr(dst, operand.rn(), operand.offset(), cond);
2477 const Condition cond) {
2480 // cond(31-28) | 1101(27-24)| U001(23-20) | Rbase(19-16) |
2492 emit(cond | u * B23 | d * B22 | 0xD1 * B20 | base.code() * B16 | sd * B12 |
2505 emit(cond | d * B22 | 0xD1 * B20 | scratch.code() * B16 | sd * B12 |
2511 const Condition cond) {
2518 vldr(dst, scratch, 0, cond);
2520 vldr(dst, operand.rn(), operand.offset(), cond);
2525 const Condition cond) {
2528 // cond(31-28) | 1101(27-24)| U(23) | D(22) | 00(21-20) | Rbase(19-16) |
2542 emit(cond | 0xD * B24 | u * B23 | d * B22 | base.code() * B16 | vd * B12 |
2555 emit(cond | 0xD * B24 | d * B22 | scratch.code() * B16 | vd * B12 |
2561 const Condition cond) {
2569 vstr(src, scratch, 0, cond);
2571 vstr(src, operand.rn(), operand.offset(), cond);
2576 const Condition cond) {
2579 // cond(31-28) | 1101(27-24)| U000(23-20) | Rbase(19-16) |
2591 emit(cond | u * B23 | d * B22 | 0xD0 * B20 | base.code() * B16 | sd * B12 |
2604 emit(cond | d * B22 | 0xD0 * B20 | scratch.code() * B16 | sd * B12 |
2610 const Condition cond) {
2617 vstr(src, scratch, 0, cond);
2619 vstr(src, operand.rn(), operand.offset(), cond);
2624 DwVfpRegister last, Condition cond) {
2626 // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) |
2637 emit(cond | B27 | B26 | am | d * B22 | B20 | base.code() * B16 | sd * B12 |
2642 DwVfpRegister last, Condition cond) {
2644 // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) |
2655 emit(cond | B27 | B26 | am | d * B22 | base.code() * B16 | sd * B12 |
2660 SwVfpRegister last, Condition cond) {
2662 // cond(31-28) | 110(27-25)| PUDW1(24-20) | Rbase(19-16) |
2671 emit(cond | B27 | B26 | am | d * B22 | B20 | base.code() * B16 | sd * B12 |
2676 SwVfpRegister last, Condition cond) {
2678 // cond(31-28) | 110(27-25)| PUDW0(24-20) | Rbase(19-16) |
2687 emit(cond | B27 | B26 | am | d * B22 | base.code() * B16 | sd * B12 |
2819 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | imm4H(19-16) |
2842 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | imm4H(19-16) |
2882 const Condition cond) {
2888 emit(cond | 0xE * B24 | d * B22 | 0xB * B20 | sd * B12 | 0xA * B8 | B6 |
2893 const Condition cond) {
2896 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) |
2904 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | vd * B12 | 0x5 * B9 | B8 | B6 |
2909 const Register src2, const Condition cond) {
2912 // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) |
2918 emit(cond | 0xC * B24 | B22 | src2.code() * B16 | src1.code() * B12 |
2923 const DwVfpRegister src, const Condition cond) {
2926 // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) |
2932 emit(cond | 0xC * B24 | B22 | B20 | dst2.code() * B16 | dst1.code() * B12 |
2937 const Condition cond) {
2940 // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) |
2945 emit(cond | 0xE * B24 | sn * B16 | src.code() * B12 | 0xA * B8 | n * B7 | B4);
2949 const Condition cond) {
2952 // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) |
2957 emit(cond | 0xE * B24 | B20 | sn * B16 | dst.code() * B12 | 0xA * B8 |
3016 VFPConversionMode mode, const Condition cond) {
3025 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 1(19) | opc2(18-16) |
3042 return (cond | 0xE * B24 | B23 | D * B22 | 0x3 * B20 | B19 | opc2 * B16 |
3047 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0111(19-16) |
3050 return (cond | 0xE * B24 | B23 | D * B22 | 0x3 * B20 | 0x7 * B16 |
3056 VFPConversionMode mode, const Condition cond) {
3058 emit(EncodeVCVT(F64, dst.code(), S32, src.code(), mode, cond));
3062 VFPConversionMode mode, const Condition cond) {
3063 emit(EncodeVCVT(F32, dst.code(), S32, src.code(), mode, cond));
3067 VFPConversionMode mode, const Condition cond) {
3069 emit(EncodeVCVT(F64, dst.code(), U32, src.code(), mode, cond));
3073 VFPConversionMode mode, const Condition cond) {
3074 emit(EncodeVCVT(F32, dst.code(), U32, src.code(), mode, cond));
3078 VFPConversionMode mode, const Condition cond) {
3079 emit(EncodeVCVT(S32, dst.code(), F32, src.code(), mode, cond));
3083 VFPConversionMode mode, const Condition cond) {
3084 emit(EncodeVCVT(U32, dst.code(), F32, src.code(), mode, cond));
3088 VFPConversionMode mode, const Condition cond) {
3090 emit(EncodeVCVT(S32, dst.code(), F64, src.code(), mode, cond));
3094 VFPConversionMode mode, const Condition cond) {
3096 emit(EncodeVCVT(U32, dst.code(), F64, src.code(), mode, cond));
3100 VFPConversionMode mode, const Condition cond) {
3102 emit(EncodeVCVT(F64, dst.code(), F32, src.code(), mode, cond));
3106 VFPConversionMode mode, const Condition cond) {
3108 emit(EncodeVCVT(F32, dst.code(), F64, src.code(), mode, cond));
3112 const Condition cond) {
3114 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 1010(19-16) | Vd(15-12) |
3124 emit(cond | 0xE * B24 | B23 | d * B22 | 0x3 * B20 | B19 | 0x2 * B16 |
3129 const Condition cond) {
3131 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) |
3140 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | B16 | vd * B12 | 0x5 * B9 |
3145 const Condition cond) {
3147 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0001(19-16) | Vd(15-12) |
3154 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | B16 | vd * B12 | 0x5 * B9 |
3159 const Condition cond) {
3161 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) |
3169 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | vd * B12 | 0x5 * B9 | B8 | B7 |
3174 const Condition cond) {
3176 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) |
3182 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | vd * B12 | 0x5 * B9 | B7 | B6 |
3187 const DwVfpRegister src2, const Condition cond) {
3191 // cond(31-28) | 11100(27-23)| D(22) | 11(21-20) | Vn(19-16) |
3202 emit(cond | 0x1C * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 |
3207 const SwVfpRegister src2, const Condition cond) {
3211 // cond(31-28) | 11100(27-23)| D(22) | 11(21-20) | Vn(19-16) |
3219 emit(cond | 0x1C * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 |
3224 const DwVfpRegister src2, const Condition cond) {
3228 // cond(31-28) | 11100(27-23)| D(22) | 11(21-20) | Vn(19-16) |
3239 emit(cond | 0x1C * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 |
3244 const SwVfpRegister src2, const Condition cond) {
3248 // cond(31-28) | 11100(27-23)| D(22) | 11(21-20) | Vn(19-16) |
3256 emit(cond | 0x1C * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 |
3261 const DwVfpRegister src2, const Condition cond) {
3265 // cond(31-28) | 11100(27-23)| D(22) | 10(21-20) | Vn(19-16) |
3276 emit(cond | 0x1C * B23 | d * B22 | 0x2 * B20 | vn * B16 | vd * B12 |
3281 const SwVfpRegister src2, const Condition cond) {
3285 // cond(31-28) | 11100(27-23)| D(22) | 10(21-20) | Vn(19-16) |
3293 emit(cond | 0x1C * B23 | d * B22 | 0x2 * B20 | vn * B16 | vd * B12 |
3298 const DwVfpRegister src2, const Condition cond) {
3300 // cond(31-28) | 11100(27-23) | D(22) | 00(21-20) | Vn(19-16) |
3311 emit(cond | 0x1C * B23 | d * B22 | vn * B16 | vd * B12 | 0x5 * B9 | B8 |
3316 const SwVfpRegister src2, const Condition cond) {
3318 // cond(31-28) | 11100(27-23) | D(22) | 00(21-20) | Vn(19-16) |
3326 emit(cond | 0x1C * B23 | d * B22 | vn * B16 | vd * B12 | 0x5 * B9 | n * B7 |
3331 const DwVfpRegister src2, const Condition cond) {
3333 // cond(31-28) | 11100(27-23) | D(22) | 00(21-20) | Vn(19-16) |
3344 emit(cond | 0x1C * B23 | d * B22 | vn * B16 | vd * B12 | 0x5 * B9 | B8 |
3349 const SwVfpRegister src2, const Condition cond) {
3351 // cond(31-28) | 11100(27-23) | D(22) | 00(21-20) | Vn(19-16) |
3359 emit(cond | 0x1C * B23 | d * B22 | vn * B16 | vd * B12 | 0x5 * B9 | n * B7 |
3364 const DwVfpRegister src2, const Condition cond) {
3368 // cond(31-28) | 11101(27-23)| D(22) | 00(21-20) | Vn(19-16) |
3379 emit(cond | 0x1D * B23 | d * B22 | vn * B16 | vd * B12 | 0x5 * B9 | B8 |
3384 const SwVfpRegister src2, const Condition cond) {
3388 // cond(31-28) | 11101(27-23)| D(22) | 00(21-20) | Vn(19-16) |
3396 emit(cond | 0x1D * B23 | d * B22 | vn * B16 | vd * B12 | 0x5 * B9 | n * B7 |
3401 const Condition cond) {
3404 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0100(19-16) |
3412 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x4 * B16 | vd * B12 |
3417 const Condition cond) {
3420 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0100(19-16) |
3426 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x4 * B16 | vd * B12 |
3431 const Condition cond) {
3434 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0101(19-16) |
3440 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x5 * B16 | vd * B12 |
3445 const Condition cond) {
3448 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0101(19-16) |
3453 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x5 * B16 | vd * B12 |
3521 void Assembler::vsel(Condition cond, const DwVfpRegister dst,
3523 // cond=kSpecialCondition(31-28) | 11100(27-23) | D(22) |
3541 int vsel_cond = (cond >> 30) & 0x3;
3542 if ((cond != eq) && (cond != ge) && (cond != gt) && (cond != vs)) {
3544 DCHECK((cond == ne) | (cond == lt) | (cond == le) | (cond == vc));
3553 void Assembler::vsel(Condition cond, const SwVfpRegister dst,
3555 // cond=kSpecialCondition(31-28) | 11100(27-23) | D(22) |
3573 int vsel_cond = (cond >> 30) & 0x3;
3574 if ((cond != eq) && (cond != ge) && (cond != gt) && (cond != vs)) {
3576 DCHECK((cond == ne) | (cond == lt) | (cond == le) | (cond == vc));
3586 const Condition cond) {
3588 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0001(19-16) |
3596 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | B16 | vd * B12 | 0x5 * B9 |
3601 const Condition cond) {
3603 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 0001(19-16) |
3609 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | B16 | vd * B12 | 0x5 * B9 |
3613 void Assembler::vmsr(Register dst, Condition cond) {
3615 // cond(31-28) | 1110 (27-24) | 1110(23-20)| 0001 (19-16) |
3617 emit(cond | 0xE * B24 | 0xE * B20 | B16 | dst.code() * B12 | 0xA * B8 | B4);
3620 void Assembler::vmrs(Register dst, Condition cond) {
3622 // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) |
3624 emit(cond | 0xE * B24 | 0xF * B20 | B16 | dst.code() * B12 | 0xA * B8 | B4);
3628 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3641 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3654 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3667 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3680 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3693 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3706 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3719 // cond=kSpecialCondition(31-28) | 11101(27-23)| D(22) | 11(21-20) |
3732 const Condition cond) {
3733 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 011(19-17) | 0(16) |
3740 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x3 * B17 | vd * B12 |
3745 const Condition cond) {
3746 // cond(31-28) | 11101(27-23)| D(22) | 11(21-20) | 011(19-17) | 0(16) |
3753 emit(cond | 0x1D * B23 | d * B22 | 0x3 * B20 | 0x3 * B17 | vd * B12 |