Lines Matching refs:pipeline
314 panvk_per_arch(emit_ubos)(const struct panvk_pipeline *pipeline,
324 if (pipeline->layout->push_constants.size) {
326 ALIGN_POT(pipeline->layout->push_constants.size, 16),
332 for (unsigned s = 0; s < pipeline->layout->vk.set_count; s++) {
334 vk_to_panvk_descriptor_set_layout(pipeline->layout->vk.set_layouts[s]);
338 panvk_pipeline_layout_ubo_start(pipeline->layout, s, false);
348 panvk_pipeline_layout_ubo_start(pipeline->layout, s, true);
352 &state->dyn.ubos[pipeline->layout->sets[s].dyn_ubo_offset + i];
370 panvk_per_arch(emit_vertex_job)(const struct panvk_pipeline *pipeline,
383 cfg.state = pipeline->rsds[MESA_SHADER_VERTEX];
400 panvk_per_arch(emit_compute_job)(const struct panvk_pipeline *pipeline,
408 pipeline->cs.local_size.x,
409 pipeline->cs.local_size.y,
410 pipeline->cs.local_size.z,
415 util_logbase2_ceil(pipeline->cs.local_size.x + 1) +
416 util_logbase2_ceil(pipeline->cs.local_size.y + 1) +
417 util_logbase2_ceil(pipeline->cs.local_size.z + 1);
421 cfg.state = pipeline->rsds[MESA_SHADER_COMPUTE];
433 panvk_emit_tiler_primitive(const struct panvk_pipeline *pipeline,
438 cfg.draw_mode = pipeline->ia.topology;
439 if (pipeline->ia.writes_point_size)
443 if (pipeline->ia.primitive_restart)
466 panvk_emit_tiler_primitive_size(const struct panvk_pipeline *pipeline,
471 if (pipeline->ia.writes_point_size) {
480 panvk_emit_tiler_dcd(const struct panvk_pipeline *pipeline,
485 cfg.front_face_ccw = pipeline->rast.front_ccw;
486 cfg.cull_front_face = pipeline->rast.cull_front_face;
487 cfg.cull_back_face = pipeline->rast.cull_back_face;
501 if (pipeline->ia.topology == MALI_DRAW_MODE_LINES ||
502 pipeline->ia.topology == MALI_DRAW_MODE_LINE_STRIP ||
503 pipeline->ia.topology == MALI_DRAW_MODE_LINE_LOOP) {
520 panvk_per_arch(emit_tiler_job)(const struct panvk_pipeline *pipeline,
530 panvk_emit_tiler_primitive(pipeline, draw, section);
533 panvk_emit_tiler_primitive_size(pipeline, draw, section);
536 panvk_emit_tiler_dcd(pipeline, draw, section);
606 const struct panvk_pipeline *pipeline,
609 const struct pan_blend_state *blend = &pipeline->blend.state;
660 bifrost_blend_type_from_nir(pipeline->fs.info.bifrost.blend[rt].type);
667 const struct panvk_pipeline *pipeline,
671 float constant = constants[pipeline->blend.constant[rt].index];
675 cfg.constant = constant * pipeline->blend.constant[rt].bifrost_factor;
680 panvk_per_arch(emit_dyn_fs_rsd)(const struct panvk_pipeline *pipeline,
685 if (pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
691 if (pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
696 if (pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
701 if (pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
710 const struct panvk_pipeline *pipeline,
713 const struct pan_shader_info *info = &pipeline->fs.info;
716 if (pipeline->fs.required) {
717 pan_shader_prepare_rsd(info, pipeline->fs.address, &cfg);
719 uint8_t rt_written = pipeline->fs.info.outputs_written >> FRAG_RESULT_DATA0;
720 uint8_t rt_mask = pipeline->fs.rt_mask;
722 pipeline->fs.info.fs.can_fpk &&
724 !pipeline->ms.alpha_to_coverage &&
725 !pipeline->blend.reads_dest;
727 bool writes_zs = pipeline->zs.z_write || pipeline->zs.s_test;
728 bool zs_always_passes = !pipeline->zs.z_test && !pipeline->zs.s_test;
733 pipeline->ms.alpha_to_coverage, zs_always_passes);
744 bool msaa = pipeline->ms.rast_samples > 1;
747 msaa ? pipeline->ms.sample_mask : UINT16_MAX;
750 pipeline->zs.z_test ? pipeline->zs.z_compare_func : MALI_FUNC_ALWAYS;
752 cfg.multisample_misc.depth_write_mask = pipeline->zs.z_write;
753 cfg.multisample_misc.fixed_function_near_discard = !pipeline->rast.clamp_depth;
754 cfg.multisample_misc.fixed_function_far_discard = !pipeline->rast.clamp_depth;
757 cfg.stencil_mask_misc.stencil_enable = pipeline->zs.s_test;
758 cfg.stencil_mask_misc.alpha_to_coverage = pipeline->ms.alpha_to_coverage;
760 cfg.stencil_mask_misc.front_facing_depth_bias = pipeline->rast.depth_bias.enable;
761 cfg.stencil_mask_misc.back_facing_depth_bias = pipeline->rast.depth_bias.enable;
762 cfg.stencil_mask_misc.single_sampled_lines = pipeline->ms.rast_samples <= 1;
764 if (!(pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))) {
765 cfg.depth_units = pipeline->rast.depth_bias.constant_factor * 2.0f;
766 cfg.depth_factor = pipeline->rast.depth_bias.slope_factor;
767 cfg.depth_bias_clamp = pipeline->rast.depth_bias.clamp;
770 if (!(pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))) {
771 cfg.stencil_front.mask = pipeline->zs.s_front.compare_mask;
772 cfg.stencil_back.mask = pipeline->zs.s_back.compare_mask;
775 if (!(pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))) {
776 cfg.stencil_mask_misc.stencil_mask_front = pipeline->zs.s_front.write_mask;
777 cfg.stencil_mask_misc.stencil_mask_back = pipeline->zs.s_back.write_mask;
780 if (!(pipeline->dynamic_state_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))) {
781 cfg.stencil_front.reference_value = pipeline->zs.s_front.ref;
782 cfg.stencil_back.reference_value = pipeline->zs.s_back.ref;
785 cfg.stencil_front.compare_function = pipeline->zs.s_front.compare_func;
786 cfg.stencil_front.stencil_fail = pipeline->zs.s_front.fail_op;
787 cfg.stencil_front.depth_fail = pipeline->zs.s_front.z_fail_op;
788 cfg.stencil_front.depth_pass = pipeline->zs.s_front.pass_op;
789 cfg.stencil_back.compare_function = pipeline->zs.s_back.compare_func;
790 cfg.stencil_back.stencil_fail = pipeline->zs.s_back.fail_op;
791 cfg.stencil_back.depth_fail = pipeline->zs.s_back.z_fail_op;
792 cfg.stencil_back.depth_pass = pipeline->zs.s_back.pass_op;