Lines Matching refs:vadd
1006 * will be vadd) */
1097 midgard_instruction **vadd,
1108 midgard_instruction **units[] = { smul, vadd, vlut };
1175 midgard_instruction *vadd = NULL;
1189 vadd = cond;
1228 vadd = ralloc(ctx, midgard_instruction);
1229 *vadd = v_mov(~0, make_compiler_temp(ctx));
1232 vadd->op = midgard_alu_op_iadd;
1233 vadd->src[0] = SSA_FIXED_REGISTER(31);
1234 vadd->src_types[0] = nir_type_uint32;
1237 vadd->swizzle[0][c] = COMPONENT_X;
1239 vadd->has_inline_constant = true;
1240 vadd->inline_constant = 0;
1242 vadd->src[1] = SSA_FIXED_REGISTER(1);
1243 vadd->src_types[0] = nir_type_uint32;
1246 vadd->swizzle[1][c] = COMPONENT_W;
1249 vadd->unit = UNIT_VADD;
1250 vadd->mask = 0x1;
1251 branch->dest = vadd->dest;
1252 branch->dest_type = vadd->dest_type;
1256 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, false);
1259 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true);
1268 mir_choose_alu(&vadd, instructions, liveness, worklist, len, &predicate, UNIT_VADD);
1275 mir_update_worklist(worklist, len, instructions, vadd);
1278 bool vadd_csel = vadd && OP_IS_CSEL(vadd->op);
1282 midgard_instruction *ins = vadd_csel ? vadd : smul;
1299 midgard_instruction *stages[] = { sadd, vadd, smul, vlut };
1372 midgard_instruction *stages[] = { vmul, sadd, vadd, smul, vlut, branch };