Lines Matching refs:sadd
1002 * condition must be in the former pipeline stage (vmul/sadd),
1178 midgard_instruction *sadd = NULL;
1197 * this will be in sadd, we boost this to prevent scheduling csel into
1201 sadd = ralloc(ctx, midgard_instruction);
1202 *sadd = v_mov(~0, make_compiler_temp(ctx));
1203 sadd->unit = UNIT_SADD;
1204 sadd->mask = 0x1;
1205 sadd->has_inline_constant = true;
1206 sadd->inline_constant = branch->constants.u32[0];
1207 branch->src[1] = sadd->dest;
1208 branch->src_types[1] = sadd->dest_type;
1217 * since we might not have room for a conditional in vmul/sadd.
1288 sadd = cond;
1293 /* Stage 2, let's schedule sadd before vmul for writeout */
1294 mir_choose_alu(&sadd, instructions, liveness, worklist, len, &predicate, UNIT_SADD);
1299 midgard_instruction *stages[] = { sadd, vadd, smul, vlut };
1365 mir_update_worklist(worklist, len, instructions, sadd);
1372 midgard_instruction *stages[] = { vmul, sadd, vadd, smul, vlut, branch };