Lines Matching refs:instructions
32 /* Scheduling for Midgard is complicated, to say the least. ALU instructions
40 * instructions can execute on SADD/SMUL units. Units on a given line execute
45 * all of the instructions within a bundle.
54 * Load/store instructions are also in bundles of simply two instructions, and
55 * texture instructions have no bundling.
66 add_dependency(struct util_dynarray *table, unsigned index, uint16_t mask, midgard_instruction **instructions, unsigned child)
75 BITSET_WORD *dependents = instructions[*parent]->dependents;
82 instructions[child]->nr_dependencies++;
99 mir_create_dependency_graph(midgard_instruction **instructions, unsigned count, unsigned node_count)
113 instructions[i]->dependents =
116 instructions[i]->nr_dependencies = 0;
123 if (instructions[i]->compact_branch)
126 unsigned dest = instructions[i]->dest;
127 unsigned mask = mir_bytemask(instructions[i]);
129 mir_foreach_src((*instructions), s) {
130 unsigned src = instructions[i]->src[s];
133 unsigned readmask = mir_bytemask_of_read_components(instructions[i], src);
134 add_dependency(last_write, src, readmask, instructions, i);
140 if (instructions[i]->type == TAG_LOAD_STORE_4 &&
141 load_store_opcode_props[instructions[i]->op].props & LDST_ADDRESS) {
143 unsigned type = instructions[i]->load_store.arg_reg |
144 instructions[i]->load_store.arg_comp;
156 BITSET_WORD *dependents = instructions[prev]->dependents;
163 instructions[i]->nr_dependencies++;
170 add_dependency(last_read, dest, mask, instructions, i);
171 add_dependency(last_write, dest, mask, instructions, i);
175 mir_foreach_src((*instructions), s) {
176 unsigned src = instructions[i]->src[s];
179 unsigned readmask = mir_bytemask_of_read_components(instructions[i], src);
185 /* If there is a branch, all instructions depend on it, as interblock
188 if (instructions[count - 1]->compact_branch) {
189 BITSET_WORD *dependents = instructions[count - 1]->dependents;
196 instructions[i]->nr_dependencies++;
276 *len = list_length(&block->base.instructions);
281 midgard_instruction **instructions =
287 instructions[i++] = ins;
289 return instructions;
292 /* The worklist is the set of instructions that can be scheduled now; that is,
293 * the set of instructions with no remaining dependencies */
296 mir_initialize_worklist(BITSET_WORD *worklist, midgard_instruction **instructions, unsigned count)
299 if (instructions[i]->nr_dependencies == 0)
311 midgard_instruction **instructions, midgard_instruction *done)
333 assert(instructions[i]->nr_dependencies);
335 if (!(--instructions[i]->nr_dependencies))
342 /* While scheduling, we need to choose instructions satisfying certain
344 * worklist to simulate in-order scheduling. Chosen instructions must satisfy a
369 /* Don't schedule instructions consuming conditionals (since we already
380 /* Whether to not-care/only/never schedule imov/fmov instructions This
381 * allows non-move instructions to get priority on each unit */
385 * scheduled instructions cannot use more than the 256-bits of pipeline
656 midgard_instruction **instructions,
699 if (tag != ~0 && instructions[i]->type != tag)
702 bool alu = (instructions[i]->type == TAG_ALU_4);
703 bool ldst = (instructions[i]->type == TAG_LOAD_STORE_4);
707 (instructions[i]->op == midgard_alu_op_imov ||
708 instructions[i]->op == midgard_alu_op_fmov);
710 if (predicate->exclude != ~0 && instructions[i]->dest == predicate->exclude)
713 if (alu && !branch && unit != ~0 && !(mir_has_unit(instructions[i], unit)))
720 if (branch && !instructions[i]->compact_branch)
723 if (alu && scalar && !mir_is_scalar(instructions[i]))
726 if (alu && predicate->constants && !mir_adjust_constants(instructions[i], predicate, false))
729 if (needs_dest && instructions[i]->dest != dest)
732 if (mask && ((~instructions[i]->mask) & mask))
735 if (instructions[i]->mask & predicate->no_mask)
738 if (ldst && mir_pipeline_count(instructions[i]) + predicate->pipeline_count > 2)
741 bool conditional = alu && !branch && OP_IS_CSEL(instructions[i]->op);
742 conditional |= (branch && instructions[i]->branch.conditional);
747 int effect = mir_live_effect(liveness, instructions[i], false);
767 midgard_instruction *I = instructions[best_index];
773 mir_adjust_constants(instructions[best_index], predicate, true);
776 predicate->pipeline_count += mir_pipeline_count(instructions[best_index]);
779 mir_adjust_unit(instructions[best_index], unit);
783 mir_live_effect(liveness, instructions[best_index], true);
789 /* Still, we don't choose instructions in a vacuum. We need a way to choose the
794 midgard_instruction **instructions,
810 midgard_instruction *chosen = mir_choose_instruction(instructions, liveness, worklist, count, &predicate);
818 chosen = mir_choose_instruction(instructions, liveness, worklist, count, &predicate);
824 chosen = mir_choose_instruction(instructions, liveness, worklist, count, &predicate);
842 midgard_instruction **instructions,
854 *slot = mir_choose_instruction(instructions, liveness, worklist, len, predicate);
878 midgard_instruction **instructions,
889 if (instructions[i]->dest != cond)
893 if (instructions[i]->type != TAG_ALU_4)
897 if (OP_IS_CSEL(instructions[i]->op))
903 if (GET_CHANNEL_COUNT(alu_opcode_props[instructions[i]->op].props))
908 if (!mir_adjust_constants(instructions[i], predicate, false))
921 mir_adjust_constants(instructions[ret], predicate, true);
933 midgard_instruction **instructions,
942 mir_comparison_mobile(ctx, instructions, predicate, count, cond) : ~0;
948 return instructions[comp_i];
960 /* Most generally, we need instructions writing to r31 in the appropriate
967 midgard_instruction **instructions,
980 ctx, instructions, predicate, worklist, count, last->src[condition_index],
1020 midgard_instruction **instructions,
1032 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1034 mir_update_worklist(worklist, len, instructions, ins);
1042 .instructions = { ins }
1050 midgard_instruction **instructions,
1064 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1067 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1074 .instructions = { ins, pair }
1080 * instructions run concurrently (TODO: verify it's not pipelined) */
1082 mir_update_worklist(worklist, len, instructions, ins);
1083 mir_update_worklist(worklist, len, instructions, pair);
1092 midgard_instruction **instructions,
1117 mir_choose_instruction(instructions, liveness, worklist, len, predicate);
1159 midgard_instruction **instructions,
1181 mir_choose_alu(&branch, instructions, liveness, worklist, len, &predicate, ALU_ENAB_BR_COMPACT);
1182 mir_update_worklist(worklist, len, instructions, branch);
1186 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);
1256 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, false);
1259 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true);
1261 mir_choose_alu(&smul, instructions, liveness, worklist, len, &predicate, UNIT_SMUL);
1266 mir_choose_alu(&vlut, instructions, liveness, worklist, len, &predicate, UNIT_VLUT);
1268 mir_choose_alu(&vadd, instructions, liveness, worklist, len, &predicate, UNIT_VADD);
1274 mir_update_worklist(worklist, len, instructions, vlut);
1275 mir_update_worklist(worklist, len, instructions, vadd);
1276 mir_update_worklist(worklist, len, instructions, smul);
1283 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, ins);
1294 mir_choose_alu(&sadd, instructions, liveness, worklist, len, &predicate, UNIT_SADD);
1327 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1362 mir_choose_alu(&vmul, instructions, liveness, worklist, len, &predicate, UNIT_VMUL);
1364 mir_update_worklist(worklist, len, instructions, vmul);
1365 mir_update_worklist(worklist, len, instructions, sadd);
1378 bundle.instructions[bundle.instruction_count++] = stages[i];
1426 midgard_instruction **instructions = flatten_mir(block, &len);
1433 mir_create_dependency_graph(instructions, len, node_count);
1439 mir_initialize_worklist(worklist, instructions, len);
1441 /* Count the number of load/store instructions so we know when it's
1445 if (instructions[i]->type == TAG_LOAD_STORE_4)
1455 unsigned tag = mir_choose_bundle(instructions, liveness, worklist, len, num_ldst);
1459 bundle = mir_schedule_texture(instructions, liveness, worklist, len, ctx->stage != MESA_SHADER_FRAGMENT);
1461 bundle = mir_schedule_ldst(instructions, liveness, worklist, len, &num_ldst);
1463 bundle = mir_schedule_alu(ctx, instructions, liveness, worklist, len);
1468 bundle.instructions[i]->bundle_id =
1488 /* Reorder instructions to match bundled. First remove existing
1489 * instructions and then recreate the list */
1496 list_add(&ins->link, &block->base.instructions);
1499 free(instructions); /* Allocated by flatten_mir() */
1537 if (list_is_empty(&blk->base.instructions))