Lines Matching refs:ctx
877 compiler_context *ctx,
883 if (!mir_single_use(ctx, cond))
932 compiler_context *ctx,
942 mir_comparison_mobile(ctx, instructions, predicate, count, cond) : ~0;
957 return mir_insert_instruction_before(ctx, user, mov);
964 mir_schedule_condition(compiler_context *ctx,
980 ctx, instructions, predicate, worklist, count, last->src[condition_index],
1090 compiler_context *ctx,
1132 midgard_instruction *mov = ralloc(ctx, midgard_instruction);
1133 *mov = v_mov(src, make_compiler_temp(ctx));
1158 compiler_context *ctx,
1186 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);
1200 if (writeout && (branch->constants.u32[0] || ctx->inputs->is_blend)) {
1201 sadd = ralloc(ctx, midgard_instruction);
1202 *sadd = v_mov(~0, make_compiler_temp(ctx));
1227 if (writeout && (ctx->inputs->is_blend || ctx->writeout_branch[1])) {
1228 vadd = ralloc(ctx, midgard_instruction);
1229 *vadd = v_mov(~0, make_compiler_temp(ctx));
1231 if (!ctx->inputs->is_blend) {
1256 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, false);
1259 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true);
1283 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, ins);
1342 unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx);
1344 vmul = ralloc(ctx, midgard_instruction);
1408 if ((writeout || tilebuf_wait) && !(ctx->quirks & MIDGARD_NO_UPPER_ALU))
1422 schedule_block(compiler_context *ctx, midgard_block *block)
1432 unsigned node_count = ctx->temp_count + 1;
1459 bundle = mir_schedule_texture(instructions, liveness, worklist, len, ctx->stage != MESA_SHADER_FRAGMENT);
1463 bundle = mir_schedule_alu(ctx, instructions, liveness, worklist, len);
1469 ctx->quadword_count + block->quadword_count;
1486 ctx->quadword_count += block->quadword_count;
1506 mir_lower_ldst(compiler_context *ctx)
1508 mir_foreach_instr_global_safe(ctx, I) {
1516 unsigned temp = make_compiler_temp(ctx);
1523 mir_insert_instruction_before(ctx, I, mov);
1532 mir_lower_blend_input(compiler_context *ctx)
1534 mir_foreach_block(ctx, _blk) {
1548 if (src >= ctx->temp_count)
1554 unsigned temp = make_compiler_temp(ctx);
1558 mir_insert_instruction_before(ctx, I, mov);
1565 midgard_schedule_program(compiler_context *ctx)
1567 mir_lower_ldst(ctx);
1568 midgard_promote_uniforms(ctx);
1571 mir_squeeze_index(ctx);
1572 mir_lower_special_reads(ctx);
1574 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1575 mir_invalidate_liveness(ctx);
1576 mir_compute_liveness(ctx);
1577 mir_lower_blend_input(ctx);
1580 mir_squeeze_index(ctx);
1584 mir_foreach_block(ctx, _block) {
1586 midgard_opt_dead_move_eliminate(ctx, block);
1587 schedule_block(ctx, block);