Lines Matching defs:unit
240 /* Only 16/32-bit can run on a scalar unit */
260 if (ains->unit & UNITS_ANY_VECTOR)
262 else if (ains->unit == ALU_ENAB_BRANCH)
354 /* For ALU, choose only this unit */
355 unsigned unit;
381 * allows non-move instructions to get priority on each unit */
580 mir_adjust_unit(midgard_instruction *ins, unsigned unit)
583 if (mir_is_add_2(ins) && (unit & (UNITS_MUL | UNIT_VLUT))) {
596 mir_has_unit(midgard_instruction *ins, unsigned unit)
598 if (alu_opcode_props[ins->op].props & unit)
663 unsigned unit = predicate->unit;
664 bool scalar = (unit != ~0) && (unit & UNITS_SCALAR);
705 bool branch = alu && (unit == ALU_ENAB_BR_COMPACT);
713 if (alu && !branch && unit != ~0 && !(mir_has_unit(instructions[i], unit)))
779 mir_adjust_unit(instructions[best_index], unit);
805 .unit = ~0,
839 /* We want to choose an ALU instruction filling a given unit */
846 unsigned unit)
853 predicate->unit = unit;
856 /* Store unit upon scheduling */
858 (*slot)->unit = unit;
1001 /* Schedule the unit: csel is always in the latter pipeline, so a csel
1009 cond->unit = UNIT_SMUL;
1011 cond->unit = vector ? UNIT_VMUL : UNIT_SADD;
1115 predicate->unit = unit_names[i];
1120 ins->unit = unit_names[i];
1148 mov->unit = unit_names[i];
1153 unreachable("Could not schedule Z/S move to any unit");
1188 if (cond->unit == UNIT_VADD)
1190 else if (cond->unit == UNIT_SMUL)
1203 sadd->unit = UNIT_SADD;
1249 vadd->unit = UNIT_VADD;
1285 if (cond->unit == UNIT_VMUL)
1287 else if (cond->unit == UNIT_SADD)
1322 predicate.unit = UNIT_VMUL;
1331 vmul->unit = UNIT_VMUL;
1346 vmul->unit = UNIT_VMUL;
1376 bundle.control |= stages[i]->unit;