Lines Matching defs:len
274 flatten_mir(midgard_block *block, unsigned *len)
276 *len = list_length(&block->base.instructions);
278 if (!(*len))
282 calloc(sizeof(midgard_instruction *), *len);
844 BITSET_WORD *worklist, unsigned len,
854 *slot = mir_choose_instruction(instructions, liveness, worklist, len, predicate);
1022 BITSET_WORD *worklist, unsigned len,
1032 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1034 mir_update_worklist(worklist, len, instructions, ins);
1052 BITSET_WORD *worklist, unsigned len,
1064 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1067 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1082 mir_update_worklist(worklist, len, instructions, ins);
1083 mir_update_worklist(worklist, len, instructions, pair);
1094 BITSET_WORD *worklist, unsigned len,
1117 mir_choose_instruction(instructions, liveness, worklist, len, predicate);
1161 BITSET_WORD *worklist, unsigned len)
1181 mir_choose_alu(&branch, instructions, liveness, worklist, len, &predicate, ALU_ENAB_BR_COMPACT);
1182 mir_update_worklist(worklist, len, instructions, branch);
1186 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);
1256 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, false);
1259 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true);
1261 mir_choose_alu(&smul, instructions, liveness, worklist, len, &predicate, UNIT_SMUL);
1266 mir_choose_alu(&vlut, instructions, liveness, worklist, len, &predicate, UNIT_VLUT);
1268 mir_choose_alu(&vadd, instructions, liveness, worklist, len, &predicate, UNIT_VADD);
1274 mir_update_worklist(worklist, len, instructions, vlut);
1275 mir_update_worklist(worklist, len, instructions, vadd);
1276 mir_update_worklist(worklist, len, instructions, smul);
1283 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, ins);
1294 mir_choose_alu(&sadd, instructions, liveness, worklist, len, &predicate, UNIT_SADD);
1327 mir_choose_instruction(instructions, liveness, worklist, len, &predicate);
1362 mir_choose_alu(&vmul, instructions, liveness, worklist, len, &predicate, UNIT_VMUL);
1364 mir_update_worklist(worklist, len, instructions, vmul);
1365 mir_update_worklist(worklist, len, instructions, sadd);
1425 unsigned len = 0;
1426 midgard_instruction **instructions = flatten_mir(block, &len);
1428 if (!len)
1433 mir_create_dependency_graph(instructions, len, node_count);
1436 size_t sz = BITSET_WORDS(len) * sizeof(BITSET_WORD);
1439 mir_initialize_worklist(worklist, instructions, len);
1444 for (unsigned i = 0; i < len; ++i) {
1455 unsigned tag = mir_choose_bundle(instructions, liveness, worklist, len, num_ldst);
1459 bundle = mir_schedule_texture(instructions, liveness, worklist, len, ctx->stage != MESA_SHADER_FRAGMENT);
1461 bundle = mir_schedule_ldst(instructions, liveness, worklist, len, &num_ldst);
1463 bundle = mir_schedule_alu(ctx, instructions, liveness, worklist, len);