Lines Matching refs:src
192 mark_node_class(alur, ins->src[0]);
193 mark_node_class(alur, ins->src[1]);
194 mark_node_class(alur, ins->src[2]);
197 mark_node_class(brar, ins->src[0]);
203 mark_node_class(ldst, ins->src[0]);
204 mark_node_class(ldst, ins->src[1]);
205 mark_node_class(ldst, ins->src[2]);
206 mark_node_class(ldst, ins->src[3]);
210 mark_node_class(texr, ins->src[0]);
211 mark_node_class(texr, ins->src[1]);
212 mark_node_class(texr, ins->src[2]);
504 unsigned s = ins->src[v];
513 unsigned s = ins->src[v];
526 if (src_size == 16 && ins->src[s] < SSA_FIXED_MINIMUM)
527 min_bound[ins->src[s]] = MAX2(min_bound[ins->src[s]], 8);
600 set_class(l->class, ins->src[0], REG_CLASS_LDST);
601 set_class(l->class, ins->src[1], REG_CLASS_LDST);
602 set_class(l->class, ins->src[2], REG_CLASS_LDST);
603 set_class(l->class, ins->src[3], REG_CLASS_LDST);
607 lcra_restrict_range(l, ins->src[0], 16);
608 lcra_restrict_range(l, ins->src[1], 16);
609 lcra_restrict_range(l, ins->src[2], 16);
610 lcra_restrict_range(l, ins->src[3], 16);
614 set_class(l->class, ins->src[0], REG_CLASS_TEXR);
615 set_class(l->class, ins->src[1], REG_CLASS_TEXR);
616 set_class(l->class, ins->src[2], REG_CLASS_TEXR);
617 set_class(l->class, ins->src[3], REG_CLASS_TEXR);
624 assert(check_read_class(l->class, ins->type, ins->src[0]));
625 assert(check_read_class(l->class, ins->type, ins->src[1]));
626 assert(check_read_class(l->class, ins->type, ins->src[2]));
627 assert(check_read_class(l->class, ins->type, ins->src[3]));
635 if (ins->src[0] < ctx->temp_count)
636 l->solutions[ins->src[0]] = 0;
638 if (ins->src[2] < ctx->temp_count)
639 l->solutions[ins->src[2]] = (16 * 1) + COMPONENT_X * 4;
641 if (ins->src[3] < ctx->temp_count)
642 l->solutions[ins->src[3]] = (16 * 1) + COMPONENT_Y * 4;
644 if (ins->src[1] < ctx->temp_count)
645 l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4;
690 used_as_r1 |= (s > 0) && (br->src[s] == ins->dest);
752 struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], src_shift[0]);
753 struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], src_shift[1]);
765 if (ins->src[0] != ~0)
766 ins->src[0] = SSA_FIXED_REGISTER(src1.reg);
767 if (ins->src[1] != ~0)
768 ins->src[1] = SSA_FIXED_REGISTER(src2.reg);
782 struct phys_reg src = index_to_reg(ctx, l, ins->src[0], src_shift[0]);
783 assert(src.reg == 26 || src.reg == 27);
785 ins->src[0] = SSA_FIXED_REGISTER(src.reg);
786 offset_swizzle(ins->swizzle[0], src.offset, src.shift, 0, 0);
798 unsigned src_index = ins->src[i];
800 struct phys_reg src = index_to_reg(ctx, l, src_index, src_shift[i]);
801 unsigned component = src.offset >> src.shift;
802 assert(component << src.shift == src.offset);
803 ins->src[i] = SSA_FIXED_REGISTER(src.reg);
817 struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], src_shift[1]);
818 struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], src_shift[2]);
819 struct phys_reg offset = index_to_reg(ctx, l, ins->src[3], src_shift[3]);
822 if (ins->src[1] != ~0)
823 ins->src[1] = SSA_FIXED_REGISTER(coord.reg);
835 if (ins->src[2] != ~0) {
837 ins->src[2] = SSA_FIXED_REGISTER(lod.reg);
842 if (ins->src[3] != ~0) {
843 ins->src[3] = SSA_FIXED_REGISTER(offset.reg);
878 lcra_set_node_spill_cost(l, ins->src[s], -1);
1102 if (ins->src[i] < min_demote || ins->src[i] >= max_demote)
1108 unsigned idx = (23 - SSA_REG_FROM_FIXED(ins->src[i])) * 4;
1118 .src = { ~0, ~0, ~0, ~0 },
1132 mir_rewrite_index_src_single(ins, ins->src[i], temp);