Lines Matching refs:ins
188 mir_foreach_instr_global(ctx, ins) {
189 switch (ins->type) {
191 mark_node_class(aluw, ins->dest);
192 mark_node_class(alur, ins->src[0]);
193 mark_node_class(alur, ins->src[1]);
194 mark_node_class(alur, ins->src[2]);
196 if (ins->compact_branch && ins->writeout)
197 mark_node_class(brar, ins->src[0]);
202 mark_node_class(aluw, ins->dest);
203 mark_node_class(ldst, ins->src[0]);
204 mark_node_class(ldst, ins->src[1]);
205 mark_node_class(ldst, ins->src[2]);
206 mark_node_class(ldst, ins->src[3]);
210 mark_node_class(texr, ins->src[0]);
211 mark_node_class(texr, ins->src[1]);
212 mark_node_class(texr, ins->src[2]);
213 mark_node_class(texw, ins->dest);
332 mir_foreach_instr_in_block_rev(block, ins) {
333 if (ins->writeout)
334 r1w = ins->dest;
341 mir_foreach_instr_global(ctx, ins) {
342 if (ins->dest < ctx->temp_count)
343 lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), r1w, 0xF);
393 mir_foreach_instr_in_block_rev(blk, ins) {
397 unsigned dest = ins->dest;
402 unsigned mask = mir_bytemask(ins);
410 if (ins->compact_branch && ins->writeout) {
424 mir_liveness_ins_update(live, ins, ctx->temp_count);
432 mir_is_64(midgard_instruction *ins)
434 if (nir_alu_type_get_type_size(ins->dest_type) == 64)
437 mir_foreach_src(ins, v) {
438 if (nir_alu_type_get_type_size(ins->src_types[v]) == 64)
495 mir_foreach_instr_global(ctx, ins) {
502 if (ins->type == TAG_ALU_4 && mir_is_64(ins)) {
503 mir_foreach_src(ins, v) {
504 unsigned s = ins->src[v];
511 if (ins->type == TAG_LOAD_STORE_4 && OP_HAS_ADDRESS(ins->op)) {
512 mir_foreach_src(ins, v) {
513 unsigned s = ins->src[v];
514 unsigned size = nir_alu_type_get_type_size(ins->src_types[v]);
524 mir_foreach_src(ins, s) {
525 unsigned src_size = nir_alu_type_get_type_size(ins->src_types[s]);
526 if (src_size == 16 && ins->src[s] < SSA_FIXED_MINIMUM)
527 min_bound[ins->src[s]] = MAX2(min_bound[ins->src[s]], 8);
533 if (ins->dest >= SSA_FIXED_MINIMUM) continue;
535 unsigned size = nir_alu_type_get_type_size(ins->dest_type);
537 if (ins->is_pack)
541 int comps1 = util_logbase2(ins->mask);
548 int dest = ins->dest;
566 if (ins->type == TAG_ALU_4 && OP_IS_CSEL_V(ins->op)) {
575 if (ins->type == TAG_LOAD_STORE_4)
596 mir_foreach_instr_global(ctx, ins) {
599 if (ins->type == TAG_LOAD_STORE_4) {
600 set_class(l->class, ins->src[0], REG_CLASS_LDST);
601 set_class(l->class, ins->src[1], REG_CLASS_LDST);
602 set_class(l->class, ins->src[2], REG_CLASS_LDST);
603 set_class(l->class, ins->src[3], REG_CLASS_LDST);
605 if (OP_IS_VEC4_ONLY(ins->op)) {
606 lcra_restrict_range(l, ins->dest, 16);
607 lcra_restrict_range(l, ins->src[0], 16);
608 lcra_restrict_range(l, ins->src[1], 16);
609 lcra_restrict_range(l, ins->src[2], 16);
610 lcra_restrict_range(l, ins->src[3], 16);
612 } else if (ins->type == TAG_TEXTURE_4) {
613 set_class(l->class, ins->dest, REG_CLASS_TEXW);
614 set_class(l->class, ins->src[0], REG_CLASS_TEXR);
615 set_class(l->class, ins->src[1], REG_CLASS_TEXR);
616 set_class(l->class, ins->src[2], REG_CLASS_TEXR);
617 set_class(l->class, ins->src[3], REG_CLASS_TEXR);
622 mir_foreach_instr_global(ctx, ins) {
623 assert(check_write_class(l->class, ins->type, ins->dest));
624 assert(check_read_class(l->class, ins->type, ins->src[0]));
625 assert(check_read_class(l->class, ins->type, ins->src[1]));
626 assert(check_read_class(l->class, ins->type, ins->src[2]));
627 assert(check_read_class(l->class, ins->type, ins->src[3]));
632 mir_foreach_instr_global(ctx, ins) {
633 if (!(ins->compact_branch && ins->writeout)) continue;
635 if (ins->src[0] < ctx->temp_count)
636 l->solutions[ins->src[0]] = 0;
638 if (ins->src[2] < ctx->temp_count)
639 l->solutions[ins->src[2]] = (16 * 1) + COMPONENT_X * 4;
641 if (ins->src[3] < ctx->temp_count)
642 l->solutions[ins->src[3]] = (16 * 1) + COMPONENT_Y * 4;
644 if (ins->src[1] < ctx->temp_count)
645 l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4;
647 if (ins->dest < ctx->temp_count)
648 l->solutions[ins->dest] = (16 * 1) + COMPONENT_W * 4;
682 midgard_instruction *ins = v->instructions[i];
684 if (ins->dest >= ctx->temp_count)
687 bool used_as_r1 = (br->dest == ins->dest);
690 used_as_r1 |= (s > 0) && (br->src[s] == ins->dest);
693 lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), node_r1, 0xFFFF);
732 midgard_instruction *ins)
738 util_logbase2(nir_alu_type_get_type_size(ins->src_types[i]) / 8);
742 util_logbase2(nir_alu_type_get_type_size(ins->dest_type) / 8);
744 switch (ins->type) {
749 if (ins->compact_branch)
752 struct phys_reg src1 = index_to_reg(ctx, l, ins->src[0], src_shift[0]);
753 struct phys_reg src2 = index_to_reg(ctx, l, ins->src[1], src_shift[1]);
754 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift);
756 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
759 GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props) ? 0 :
762 offset_swizzle(ins->swizzle[0], src1.offset, src1.shift, dest.shift, dest_offset);
763 if (!ins->has_inline_constant)
764 offset_swizzle(ins->swizzle[1], src2.offset, src2.shift, dest.shift, dest_offset);
765 if (ins->src[0] != ~0)
766 ins->src[0] = SSA_FIXED_REGISTER(src1.reg);
767 if (ins->src[1] != ~0)
768 ins->src[1] = SSA_FIXED_REGISTER(src2.reg);
769 if (ins->dest != ~0)
770 ins->dest = SSA_FIXED_REGISTER(dest.reg);
779 bool encodes_src = OP_IS_STORE(ins->op);
782 struct phys_reg src = index_to_reg(ctx, l, ins->src[0], src_shift[0]);
785 ins->src[0] = SSA_FIXED_REGISTER(src.reg);
786 offset_swizzle(ins->swizzle[0], src.offset, src.shift, 0, 0);
788 struct phys_reg dst = index_to_reg(ctx, l, ins->dest, dest_shift);
790 ins->dest = SSA_FIXED_REGISTER(dst.reg);
791 offset_swizzle(ins->swizzle[0], 0, 2, dest_shift, dst.offset);
792 mir_set_bytemask(ins, mir_bytemask(ins) << dst.offset);
798 unsigned src_index = ins->src[i];
803 ins->src[i] = SSA_FIXED_REGISTER(src.reg);
804 ins->swizzle[i][0] += component;
812 if (ins->op == midgard_tex_op_barrier)
816 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift);
817 struct phys_reg coord = index_to_reg(ctx, l, ins->src[1], src_shift[1]);
818 struct phys_reg lod = index_to_reg(ctx, l, ins->src[2], src_shift[2]);
819 struct phys_reg offset = index_to_reg(ctx, l, ins->src[3], src_shift[3]);
822 if (ins->src[1] != ~0)
823 ins->src[1] = SSA_FIXED_REGISTER(coord.reg);
824 offset_swizzle(ins->swizzle[1], coord.offset, coord.shift, dest.shift, 0);
827 if (ins->dest != ~0)
828 ins->dest = SSA_FIXED_REGISTER(dest.reg);
829 offset_swizzle(ins->swizzle[0], 0, 2, dest.shift,
832 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
835 if (ins->src[2] != ~0) {
837 ins->src[2] = SSA_FIXED_REGISTER(lod.reg);
838 ins->swizzle[2][0] = lod.offset / 4;
842 if (ins->src[3] != ~0) {
843 ins->src[3] = SSA_FIXED_REGISTER(offset.reg);
844 ins->swizzle[3][0] = offset.offset / 4;
858 mir_foreach_instr_global(ctx, ins)
859 install_registers_instr(ctx, l, ins);
872 mir_foreach_instr_global(ctx, ins) {
873 if (ins->no_spill & (1 << l->spill_class)) {
874 lcra_set_node_spill_cost(l, ins->dest, -1);
877 mir_foreach_src(ins, s)
878 lcra_set_node_spill_cost(l, ins->src[s], -1);
917 mir_foreach_instr_global_safe(ctx, ins) {
918 read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
919 if (ins->dest == spill_node)
938 mir_foreach_instr_in_block_safe(block, ins) {
939 if (ins->dest != spill_node) continue;
950 st.mask = ins->mask;
951 st.dest_type = st.src_types[1] = ins->dest_type;
956 mir_insert_instruction_after_scheduled(ctx, block, ins, st);
958 unsigned bundle = ins->bundle_id;
961 unsigned bytemask = mir_bytemask(ins);
968 mir_insert_instruction_before_scheduled(ctx, block, ins, read);
973 ins->dest = dest;
974 ins->no_spill |= (1 << spill_class);
980 midgard_instruction *it = ins;
1004 last_spill = mir_insert_instruction_after_scheduled(ctx, block, ins, st);
1008 midgard_instruction mv = v_mov(ins->dest, dest);
1011 mir_insert_instruction_after_scheduled(ctx, block, ins, mv);
1015 last_spill_index = ins->dest;
1035 mir_foreach_instr_in_block(block, ins) {
1038 if (ins->hint) continue;
1041 if (!mir_has_arg(ins, spill_node)) continue;
1048 midgard_instruction *before = ins;
1074 mir_rewrite_index_src_single(ins, spill_node, index);
1083 mir_foreach_instr_global(ctx, ins) {
1084 ins->hint = false;
1100 mir_foreach_instr_in_block(block, ins) {
1101 mir_foreach_src(ins, i) {
1102 if (ins->src[i] < min_demote || ins->src[i] >= max_demote)
1105 midgard_instruction *before = ins;
1108 unsigned idx = (23 - SSA_REG_FROM_FIXED(ins->src[i])) * 4;
1117 .dest_type = ins->src_types[i],
1132 mir_rewrite_index_src_single(ins, ins->src[i], temp);