Lines Matching refs:dest
191 mark_node_class(aluw, ins->dest);
202 mark_node_class(aluw, ins->dest);
213 mark_node_class(texw, ins->dest);
281 if (pre_use->dest != i)
334 r1w = ins->dest;
342 if (ins->dest < ctx->temp_count)
343 lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), r1w, 0xF);
375 if (ins_a->dest >= ctx->temp_count) continue;
380 if (ins_b->dest >= ctx->temp_count) continue;
382 lcra_add_node_interference(l, ins_b->dest,
384 ins_a->dest,
397 unsigned dest = ins->dest;
399 if (dest < ctx->temp_count) {
403 lcra_add_node_interference(l, dest, mask, i, live[i]);
533 if (ins->dest >= SSA_FIXED_MINIMUM) continue;
548 int dest = ins->dest;
549 found_class[dest] = MAX2(found_class[dest], bytes);
551 min_alignment[dest] =
552 MAX2(min_alignment[dest],
559 if (size == 16 && min_alignment[dest] != 4)
560 min_bound[dest] = 8;
567 min_alignment[dest] = 4; /* 1 << 4= 16-byte = vec4 */
570 min_bound[dest] = 16;
576 min_alignment[dest] = MAX2(min_alignment[dest], 2);
606 lcra_restrict_range(l, ins->dest, 16);
613 set_class(l->class, ins->dest, REG_CLASS_TEXW);
623 assert(check_write_class(l->class, ins->type, ins->dest));
647 if (ins->dest < ctx->temp_count)
648 l->solutions[ins->dest] = (16 * 1) + COMPONENT_W * 4;
684 if (ins->dest >= ctx->temp_count)
687 bool used_as_r1 = (br->dest == ins->dest);
690 used_as_r1 |= (s > 0) && (br->src[s] == ins->dest);
693 lcra_add_node_interference(l, ins->dest, mir_bytemask(ins), node_r1, 0xFFFF);
754 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift);
756 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
760 dest.offset;
762 offset_swizzle(ins->swizzle[0], src1.offset, src1.shift, dest.shift, dest_offset);
764 offset_swizzle(ins->swizzle[1], src2.offset, src2.shift, dest.shift, dest_offset);
769 if (ins->dest != ~0)
770 ins->dest = SSA_FIXED_REGISTER(dest.reg);
788 struct phys_reg dst = index_to_reg(ctx, l, ins->dest, dest_shift);
790 ins->dest = SSA_FIXED_REGISTER(dst.reg);
816 struct phys_reg dest = index_to_reg(ctx, l, ins->dest, dest_shift);
824 offset_swizzle(ins->swizzle[1], coord.offset, coord.shift, dest.shift, 0);
827 if (ins->dest != ~0)
828 ins->dest = SSA_FIXED_REGISTER(dest.reg);
829 offset_swizzle(ins->swizzle[0], 0, 2, dest.shift,
830 dest_shift == 1 ? dest.offset % 8 :
831 dest.offset);
832 mir_set_bytemask(ins, mir_bytemask(ins) << dest.offset);
874 lcra_set_node_spill_cost(l, ins->dest, -1);
919 if (ins->dest == spill_node)
939 if (ins->dest != spill_node) continue;
959 unsigned dest = (bundle == last_id)? last_spill_index : spill_index++;
967 v_load_store_scratch(dest, spill_slot, false, 0xF);
973 ins->dest = dest;
986 mir_rewrite_index_src_single(it, spill_node, dest);
995 dest = spill_index++;
1003 v_load_store_scratch(dest, spill_slot, true, write_mask);
1008 midgard_instruction mv = v_mov(ins->dest, dest);
1015 last_spill_index = ins->dest;
1116 .dest = temp,