Lines Matching defs:read
116 /* Special register classes impose special constraints on who can read their
161 * to create a bit field of types of instructions that read a particular index.
240 * (alur) can read the results of the texture pipeline (texw)
241 * but not ldst or texr. Load/store ops (ldst) cannot read
242 * anything but load/store inputs. Texture pipeline cannot read
273 /* Insert move before each read/write, depending on the
521 /* Anything read as 16-bit needs proper alignment to ensure the
660 * gl_FragDepth write so it won't show up correctly when r1 is read in
775 /* Which physical register we read off depends on
943 * we're spilling, or otherwise we'll read invalid
966 midgard_instruction read =
968 mir_insert_instruction_before_scheduled(ctx, block, ins, read);
989 * a work register for `it` to read but