Lines Matching refs:ins
78 mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
80 bool integer = midgard_is_integer_op(ins->op);
81 unsigned base_size = max_bitsize_for_alu(ins);
82 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
86 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) :
87 ((ins->src_abs[i] << 0) |
88 ((ins->src_neg[i] << 1)));
123 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
125 bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32;
127 bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16;
128 bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16;
129 unsigned comp = component_from_mask(ins->mask);
132 mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]),
133 mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp])
155 if (ins->has_inline_constant) {
157 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
197 mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu)
199 unsigned effective = ins->mask;
205 unsigned inst_size = max_bitsize_for_alu(ins);
206 signed upper_shift = mir_upper_override(ins, inst_size);
325 mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu)
327 bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props);
329 unsigned base_size = max_bitsize_for_alu(ins);
332 if (ins->has_inline_constant && (i == 1))
335 if (ins->src[i] == ~0)
338 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
342 if (sz == 8 && base_size == 8 && ins->op == midgard_alu_op_imov) {
343 ins->outmod = midgard_outmod_keeplo;
348 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
353 .mod = mir_pack_mod(ins, i, false),
368 mir_pack_swizzle_ldst(midgard_instruction *ins)
370 unsigned compsz = OP_IS_STORE(ins->op) ?
371 nir_alu_type_get_type_size(ins->src_types[0]) :
372 nir_alu_type_get_type_size(ins->dest_type);
377 unsigned v = ins->swizzle[0][c];
384 ins->load_store.swizzle |= (v / step) << (2 * (c / step));
386 ins->load_store.swizzle |= ((v / step) << (4 * c)) |
394 mir_pack_swizzle_tex(midgard_instruction *ins)
400 unsigned v = ins->swizzle[i][c];
409 ins->texture.swizzle = packed;
411 ins->texture.in_reg_swizzle = packed;
436 midgard_instruction *ins = bundle->instructions[i];
438 mir_foreach_src(ins, s) {
439 if (ins->src[s] == dependency)
449 mir_pack_tex_ooo(midgard_block *block, midgard_bundle *bundle, midgard_instruction *ins)
454 if (!mir_can_run_ooo(block, bundle + count + 1, ins->dest))
458 ins->texture.out_of_order = count;
469 midgard_pack_common_store_mask(midgard_instruction *ins) {
470 ASSERTED unsigned comp_sz = nir_alu_type_get_type_size(ins->src_types[0]);
471 unsigned bytemask = mir_bytemask(ins);
474 switch (ins->op) {
476 return mir_bytemask(ins) & 1;
478 return mir_bytemask(ins) & 3;
480 return mir_bytemask(ins);
501 mir_pack_ldst_mask(midgard_instruction *ins)
503 unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
504 unsigned packed = ins->mask;
506 if (OP_IS_COMMON_STORE(ins->op)) {
507 packed = midgard_pack_common_store_mask(ins);
510 packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) |
511 ((ins->mask & 0x1) ? (0x2 | 0x1) : 0);
518 unsigned submask = (ins->mask >> (i * comps_per_32b)) &
530 ins->load_store.mask = packed;
534 mir_lower_inverts(midgard_instruction *ins)
537 ins->src_invert[0],
538 ins->src_invert[1],
539 ins->src_invert[2]
542 switch (ins->op) {
548 ins->op = midgard_alu_op_inor;
550 ins->op = midgard_alu_op_iandnot;
558 ins->op = midgard_alu_op_inand;
560 ins->op = midgard_alu_op_iornot;
569 ins->op = midgard_alu_op_inxor;
581 mir_lower_roundmode(midgard_instruction *ins)
583 if (alu_opcode_props[ins->op].props & MIDGARD_ROUNDS) {
584 assert(ins->roundmode <= 0x3);
585 ins->op += ins->roundmode;
590 load_store_from_instr(midgard_instruction *ins)
592 midgard_load_store_word ldst = ins->load_store;
593 ldst.op = ins->op;
596 ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1;
598 ldst.reg = SSA_REG_FROM_FIXED(ins->dest);
604 if (OP_IS_ATOMIC(ins->op)) {
606 ldst.swizzle |= ins->swizzle[3][0] & 3;
607 ldst.swizzle |= (SSA_REG_FROM_FIXED(ins->src[3]) & 1 ? 1 : 0) << 2;
610 if (ins->src[1] != ~0) {
611 ldst.arg_reg = SSA_REG_FROM_FIXED(ins->src[1]) - REGISTER_LDST_BASE;
612 unsigned sz = nir_alu_type_get_type_size(ins->src_types[1]);
613 ldst.arg_comp = midgard_ldst_comp(ldst.arg_reg, ins->swizzle[1][0], sz);
616 if (ins->src[2] != ~0) {
617 ldst.index_reg = SSA_REG_FROM_FIXED(ins->src[2]) - REGISTER_LDST_BASE;
618 unsigned sz = nir_alu_type_get_type_size(ins->src_types[2]);
619 ldst.index_comp = midgard_ldst_comp(ldst.index_reg, ins->swizzle[2][0], sz);
626 texture_word_from_instr(midgard_instruction *ins)
628 midgard_texture_word tex = ins->texture;
629 tex.op = ins->op;
631 unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]);
634 unsigned dest = ins->dest == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->dest);
637 if (ins->src[2] != ~0) {
639 .select = SSA_REG_FROM_FIXED(ins->src[2]) & 1,
641 .component = ins->swizzle[2][0]
648 if (ins->src[3] != ~0) {
649 unsigned x = ins->swizzle[3][0];
656 unsigned offset_reg = SSA_REG_FROM_FIXED(ins->src[3]);
670 vector_alu_from_instr(midgard_instruction *ins)
673 .op = ins->op,
674 .outmod = ins->outmod,
675 .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins))
678 if (ins->has_inline_constant) {
682 int lower_11 = ins->inline_constant & ((1 << 12) - 1);
724 emit_branch(midgard_instruction *ins,
731 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT;
732 bool is_conditional = ins->branch.conditional;
733 bool is_inverted = ins->branch.invert_conditional;
734 bool is_discard = ins->branch.target_type == TARGET_DISCARD;
735 bool is_tilebuf_wait = ins->branch.target_type == TARGET_TILEBUF_WAIT;
737 bool is_writeout = ins->writeout;
740 int target_number = ins->branch.target_block;
820 } else { /* `ins->compact_branch`, misnomer */
845 midgard_instruction *ins = bundle->instructions[i];
848 if (ins->compact_branch) continue;
851 if (ins->has_inline_constant)
852 src2_reg = ins->inline_constant >> 11;
853 else if (ins->src[1] != ~0)
854 src2_reg = SSA_REG_FROM_FIXED(ins->src[1]);
859 .src1_reg = (ins->src[0] == ~0 ?
861 SSA_REG_FROM_FIXED(ins->src[0])),
863 .src2_imm = ins->has_inline_constant,
864 .out_reg = (ins->dest == ~0 ?
866 SSA_REG_FROM_FIXED(ins->dest)),
874 midgard_instruction *ins = bundle->instructions[i];
876 if (!ins->compact_branch) {
877 mir_lower_inverts(ins);
878 mir_lower_roundmode(ins);
881 if (midgard_is_branch_unit(ins->unit)) {
882 emit_branch(ins, ctx, block, bundle, emission);
883 } else if (ins->unit & UNITS_ANY_VECTOR) {
884 midgard_vector_alu source = vector_alu_from_instr(ins);
885 mir_pack_mask_alu(ins, &source);
886 mir_pack_vector_srcs(ins, &source);
890 midgard_scalar_alu source = vector_to_scalar_alu(vector_alu_from_instr(ins), ins);
913 mir_ldst_pack_offset(midgard_instruction *ins, int offset)
916 assert(!OP_IS_REG2REG_LDST(ins->op) ||
917 ins->op == midgard_op_lea ||
918 ins->op == midgard_op_lea_image);
920 if (OP_IS_UBO_READ(ins->op))
921 ins->load_store.signed_offset |= PACK_LDST_UBO_OFS(offset);
922 else if (OP_IS_IMAGE(ins->op))
923 ins->load_store.signed_offset |= PACK_LDST_ATTRIB_OFS(offset);
924 else if (OP_IS_SPECIAL(ins->op))
925 ins->load_store.signed_offset |= PACK_LDST_SELECTOR_OFS(offset);
927 ins->load_store.signed_offset |= PACK_LDST_MEM_OFS(offset);
976 midgard_instruction *ins = bundle->instructions[i];
977 mir_pack_ldst_mask(ins);
980 if (!OP_IS_ATOMIC(ins->op))
981 mir_pack_swizzle_ldst(ins);
984 unsigned offset = ins->constants.u32[0];
986 mir_ldst_pack_offset(ins, offset);
1018 midgard_instruction *ins = bundle->instructions[0];
1020 ins->texture.type = bundle->tag;
1021 ins->texture.next_type = next_tag;
1022 ins->texture.exec = MIDGARD_PARTIAL_EXECUTION_NONE; /* default */
1025 if (ins->op == midgard_tex_op_barrier) {
1026 ins->texture.op = ins->op;
1027 util_dynarray_append(emission, midgard_texture_word, ins->texture);
1031 signed override = mir_upper_override(ins, 32);
1033 ins->texture.mask = override > 0 ?
1034 ins->mask >> override :
1035 ins->mask;
1037 mir_pack_swizzle_tex(ins);
1040 mir_pack_tex_ooo(block, bundle, ins);
1042 unsigned osz = nir_alu_type_get_type_size(ins->dest_type);
1043 unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]);
1048 ins->texture.out_full = (osz == 32);
1049 ins->texture.out_upper = override > 0;
1050 ins->texture.in_reg_full = (isz == 32);
1051 ins->texture.sampler_type = midgard_sampler_type(ins->dest_type);
1052 ins->texture.outmod = ins->outmod;
1054 if (mir_op_computes_derivatives(ctx->stage, ins->op)) {
1055 if (ins->helper_terminate)
1056 ins->texture.exec = MIDGARD_PARTIAL_EXECUTION_KILL;
1057 else if (!ins->helper_execute)
1058 ins->texture.exec = MIDGARD_PARTIAL_EXECUTION_SKIP;
1061 midgard_texture_word texture = texture_word_from_instr(ins);