Lines Matching refs:ins
189 midgard_instruction ins = {
201 return ins;
205 attach_constants(compiler_context *ctx, midgard_instruction *ins, void *constants, int name)
207 ins->has_constants = true;
208 memcpy(&ins->constants, constants, 16);
515 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), to);
516 attach_constants(ctx, &ins, constant_value, node + 1);
517 emit_mir_instruction(ctx, ins);
545 midgard_instruction ins = emit_image_op(ctx, instr, true); \
546 emit_atomic(ctx, instr, false, midgard_op_atomic_##op, ins.dest); \
637 mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i, unsigned to, bool *abs, bool *neg, bool *not, enum midgard_roundmode *roundmode, bool is_int, unsigned bcast_count)
668 ins->src[to] = nir_src_index(NULL, &src.src);
669 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits;
672 ins->swizzle[to][c] = src.swizzle[
992 midgard_instruction ins = {
1001 &ins.roundmode : NULL;
1003 for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i)
1004 ins.src[i] = ~0;
1007 ins.src[0] = ~0;
1008 mir_copy_src(&ins, instr, 0, 1, &ins.src_abs[1], &ins.src_neg[1], &ins.src_invert[1], roundptr, is_int, broadcast_swizzle);
1029 mir_copy_src(&ins, instr, i, to, &ins.src_abs[to], &ins.src_neg[to], &ins.src_invert[to], roundptr, is_int, broadcast_swizzle);
1032 if (instr->op == nir_op_b32csel && ins.src_invert[2]) {
1033 ins.src_invert[2] = false;
1042 ins.src_neg[1] ^= true;
1045 ins.src_abs[1] = true;
1048 ins.mask = mask_of(nr_components);
1055 ins.mask &= instr->dest.write_mask;
1057 ins.op = op;
1058 ins.outmod = outmod;
1068 ins.has_inline_constant = false;
1069 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1070 ins.src_types[1] = nir_type_float32;
1071 ins.has_constants = true;
1074 ins.constants.f32[0] = 1.0f;
1076 ins.constants.i32[0] = 1;
1079 ins.swizzle[1][c] = 0;
1081 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1082 ins.src_types[1] = nir_type_float16;
1083 ins.has_constants = true;
1084 ins.constants.i16[0] = _mesa_float_to_half(1.0);
1087 ins.swizzle[1][c] = 0;
1090 ins.has_inline_constant = false;
1091 ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
1092 ins.src_types[1] = ins.src_types[0];
1093 ins.has_constants = true;
1094 ins.constants.u32[0] = 0;
1097 ins.swizzle[1][c] = 0;
1099 ins.dest_type = nir_type_uint16;
1100 ins.mask = mask_of(nr_components * 2);
1101 ins.is_pack = true;
1103 ins.dest_type = nir_type_uint8;
1104 ins.mask = mask_of(nr_components * 4);
1105 ins.is_pack = true;
1107 ins.dest_type = nir_type_uint32;
1108 ins.mask = mask_of(nr_components >> 1);
1109 ins.is_pack = true;
1111 ins.dest_type = nir_type_uint32;
1112 ins.mask = mask_of(nr_components >> 2);
1113 ins.is_pack = true;
1121 unsigned orig_mask = ins.mask;
1124 memcpy(&swizzle_back, ins.swizzle[0], sizeof(swizzle_back));
1133 ins.mask = 1 << i;
1134 ins.mask &= orig_mask;
1138 ins_split[j].mask |= ins.mask;
1139 ins.mask = 0;
1144 if (!ins.mask)
1148 ins.swizzle[0][j] = swizzle_back[i]; /* Pull from the correct component */
1150 ins_split[ins_count] = ins;
1159 emit_mir_instruction(ctx, ins);
1166 mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read)
1179 dsize = OP_IS_COMMON_STORE(ins->op) ?
1185 ins->dest_type = nir_type_uint | dsize;
1186 mir_set_bytemask(ins, bytemask);
1203 midgard_instruction ins;
1212 ins = m_ld_ubo_u8(dest, 0);
1214 ins = m_ld_ubo_u16(dest, 0);
1216 ins = m_ld_ubo_32(dest, 0);
1218 ins = m_ld_ubo_64(dest, 0);
1220 ins = m_ld_ubo_128(dest, 0);
1224 ins.constants.u32[0] = offset;
1227 mir_set_intr_mask(instr, &ins, true);
1230 ins.src[2] = nir_src_index(ctx, indirect_offset);
1231 ins.src_types[2] = nir_type_uint32;
1232 ins.load_store.index_shift = indirect_shift;
1236 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[2]); ++i)
1237 ins.swizzle[2][i] = 0;
1239 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1243 mir_set_ubo_offset(&ins, indirect_offset, offset);
1245 midgard_pack_ubo_index_imm(&ins.load_store, index);
1247 return emit_mir_instruction(ctx, ins);
1262 midgard_instruction ins;
1270 case 8: ins = m_ld_u8(srcdest, 0); break;
1271 case 16: ins = m_ld_u16(srcdest, 0); break;
1272 case 32: ins = m_ld_32(srcdest, 0); break;
1273 case 64: ins = m_ld_64(srcdest, 0); break;
1274 case 128: ins = m_ld_128(srcdest, 0); break;
1278 mir_set_intr_mask(instr, &ins, is_read);
1286 if (!(ins.mask & BITFIELD_RANGE(c, comps_per_32b)))
1291 if (ins.mask & BITFIELD_BIT(c + i)) {
1292 base = ins.swizzle[0][c + i];
1300 if (!(ins.mask & BITFIELD_BIT(c + i))) {
1301 ins.swizzle[0][c + i] = base + i;
1302 ins.mask |= BITFIELD_BIT(c + i);
1304 assert(ins.swizzle[0][c + i] == base + i);
1314 ins = m_st_u8(srcdest, 0);
1316 ins = m_st_u16(srcdest, 0);
1318 ins = m_st_32(srcdest, 0);
1320 ins = m_st_64(srcdest, 0);
1322 ins = m_st_128(srcdest, 0);
1326 mir_set_intr_mask(instr, &ins, is_read);
1329 mir_set_offset(ctx, &ins, offset, seg);
1332 assert(ins.mask);
1333 unsigned first_component = __builtin_ffs(ins.mask) - 1;
1335 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i) {
1336 if (!(ins.mask & (1 << i)))
1337 ins.swizzle[0][i] = first_component;
1340 emit_mir_instruction(ctx, ins);
1367 midgard_instruction ins = {
1383 ins.src[2] = val;
1384 ins.src_types[2] = type | bitsize;
1385 ins.src[3] = xchg_val;
1388 ins.load_store.arg_reg = REGISTER_LDST_LOCAL_STORAGE_PTR;
1389 ins.load_store.arg_comp = COMPONENT_Z;
1390 ins.load_store.bitsize_toggle = true;
1393 ins.swizzle[1][i] = i;
1395 ins.src[1] = is_image ? image_direct_address :
1397 ins.src_types[1] = nir_type_uint64;
1401 ins.swizzle[2][i] = i;
1403 ins.src[2] = image_direct_address;
1404 ins.src_types[2] = nir_type_uint64;
1406 ins.load_store.arg_reg = REGISTER_LDST_ZERO;
1407 ins.load_store.bitsize_toggle = true;
1408 ins.load_store.index_format = midgard_index_address_u64;
1410 mir_set_offset(ctx, &ins, src_offset, is_shared ? LDST_SHARED : LDST_GLOBAL);
1412 mir_set_intr_mask(&instr->instr, &ins, true);
1414 emit_mir_instruction(ctx, ins);
1427 midgard_instruction ins = m_ld_vary_32(dest, PACK_LDST_ATTRIB_OFS(offset));
1428 ins.mask = mask_of(nr_comp);
1429 ins.dest_type = type;
1433 ins.mask = mask_of(ALIGN_POT(nr_comp, 2));
1436 for (unsigned i = 0; i < ARRAY_SIZE(ins.swizzle[0]); ++i)
1437 ins.swizzle[0][i] = MIN2(i + component, COMPONENT_W);
1445 midgard_pack_varying_params(&ins.load_store, p);
1448 ins.src[2] = nir_src_index(ctx, indirect_offset);
1449 ins.src_types[2] = nir_type_uint32;
1451 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1453 ins.load_store.arg_reg = REGISTER_LDST_ZERO;
1454 ins.load_store.index_format = midgard_index_address_u32;
1460 ins.op = midgard_op_ld_vary_32u;
1463 ins.op = midgard_op_ld_vary_32i;
1466 ins.op = midgard_op_ld_vary_32;
1469 ins.op = midgard_op_ld_vary_16;
1476 emit_mir_instruction(ctx, ins);
1506 midgard_instruction ins;
1512 ins = st_image(type, val, PACK_LDST_ATTRIB_OFS(address));
1514 ins.src_types[0] = base_type | nir_src_bit_size(instr->src[3]);
1517 ins = m_lea_image(dest, PACK_LDST_ATTRIB_OFS(address));
1518 ins.mask = mask_of(2); /* 64-bit memory address */
1521 ins = ld_image(type, nir_dest_index(&instr->dest), PACK_LDST_ATTRIB_OFS(address));
1522 ins.mask = mask_of(nir_intrinsic_dest_components(instr));
1523 ins.dest_type = type;
1527 ins.src[1] = coord_reg;
1528 ins.src_types[1] = nir_type_uint16;
1530 ins.load_store.bitsize_toggle = true;
1535 ins.src[2] = nir_src_index(ctx, index);
1536 ins.src_types[2] = nir_type_uint32;
1538 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1540 emit_mir_instruction(ctx, ins);
1542 return ins;
1551 midgard_instruction ins = m_ld_attr_32(dest, PACK_LDST_ATTRIB_OFS(offset));
1552 ins.load_store.arg_reg = REGISTER_LDST_ZERO;
1553 ins.load_store.index_reg = REGISTER_LDST_ZERO;
1554 ins.mask = mask_of(nr_comp);
1560 ins.op = midgard_op_ld_attr_32u;
1563 ins.op = midgard_op_ld_attr_32i;
1566 ins.op = midgard_op_ld_attr_32;
1573 emit_mir_instruction(ctx, ins);
1592 midgard_instruction *ins =
1596 ins->mask = mask_of(nr_components);
1628 struct midgard_instruction ins =
1633 ins.writeout = depth_only ? 0 : PAN_WRITEOUT_C;
1636 ins.src[0] = src;
1637 ins.src_types[0] = nir_type_uint32;
1640 ins.constants.u32[0] = 0xFF;
1642 ins.constants.u32[0] = ((rt - MIDGARD_COLOR_RT0) << 8) | sample_iter;
1645 ins.swizzle[0][i] = i;
1649 ins.src[2] = src_z;
1650 ins.src_types[2] = nir_type_uint32;
1651 ins.writeout |= PAN_WRITEOUT_Z;
1655 ins.src[3] = src_s;
1656 ins.src_types[3] = nir_type_uint32;
1657 ins.writeout |= PAN_WRITEOUT_S;
1661 br = emit_mir_instruction(ctx, ins);
1675 midgard_instruction ins = m_ldst_mov(reg, 0);
1676 ins.mask = mask_of(3);
1677 ins.swizzle[0][3] = COMPONENT_X; /* xyzx */
1678 ins.load_store.arg_reg = compute_builtin_arg(instr->intrinsic);
1679 emit_mir_instruction(ctx, ins);
1721 midgard_instruction ins = {
1728 emit_mir_instruction(ctx, ins);
2000 midgard_instruction ins = v_mov(reg_2, out);
2001 emit_mir_instruction(ctx, ins);
2274 midgard_instruction *ins)
2289 ins->src_types[1] = nir_tex_instr_src_type(instr, coord_idx) |
2300 ins->swizzle[1][c] = COMPONENT_X;
2307 ins->swizzle[1][COMPONENT_Z] = --nr_comps;
2317 ins->swizzle[1][COMPONENT_W] = --nr_comps;
2323 assert(ins->op != midgard_tex_op_fetch);
2325 ins->src[1] = make_compiler_temp_reg(ctx);
2330 midgard_instruction ld = m_ld_cubemap_coords(ins->src[1], 0);
2332 ld.src_types[1] = ins->src_types[1];
2349 ins->swizzle[1][c] = c;
2360 if (ins->src[1] == ~0)
2361 ins->src[1] = make_compiler_temp_reg(ctx);
2363 midgard_instruction mov = v_mov(sample_or_ref, ins->src[1]);
2370 ins->swizzle[1][COMPONENT_Z] = COMPONENT_Z;
2378 if (ins->op == midgard_tex_op_fetch &&
2380 if (ins->src[1] == ~0)
2381 ins->src[1] = make_compiler_temp_reg(ctx);
2385 v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), ins->src[1]);
2391 ins->swizzle[1][c] = c;
2395 if (ins->src[1] == ~0) {
2397 ins->src[1] = coords;
2400 midgard_instruction mov = v_mov(coords, ins->src[1]);
2404 mov.swizzle[1][c] = ins->swizzle[1][c];
2405 ins->swizzle[1][c] = c;
2433 midgard_instruction ins = {
2452 ins.swizzle[0][i] = COMPONENT_X;
2461 set_tex_coord(ctx, instr, &ins);
2469 if (!is_txf && pan_attach_constant_bias(ctx, instr->src[i].src, &ins.texture))
2472 ins.texture.lod_register = true;
2473 ins.src[2] = index;
2474 ins.src_types[2] = T;
2477 ins.swizzle[2][c] = COMPONENT_X;
2485 ins.texture.offset_register = true;
2486 ins.src[3] = index;
2487 ins.src_types[3] = T;
2490 ins.swizzle[3][c] = (c > COMPONENT_Z) ? 0 : c;
2508 emit_mir_instruction(ctx, ins);
2627 midgard_instruction ins = v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT), scratch);
2628 attach_constants(ctx, &ins, entry, alu->src[1] + 1);
2634 mir_insert_instruction_before(ctx, mir_prev_op(alu), ins);
2641 max_bitsize_for_alu(midgard_instruction *ins)
2645 if (ins->src[i] == ~0) continue;
2646 unsigned src_bitsize = nir_alu_type_get_type_size(ins->src_types[i]);
2649 unsigned dst_bitsize = nir_alu_type_get_type_size(ins->dest_type);
2660 switch (ins->op) {
2677 if (midgard_is_integer_out_op(ins->op) && ins->outmod == midgard_outmod_keephi) {
2710 mir_foreach_instr_in_block(block, ins) {
2711 if (!ins->has_constants) continue;
2712 if (ins->has_inline_constant) continue;
2714 unsigned max_bitsize = max_bitsize_for_alu(ins);
2727 int op = ins->op;
2729 if (ins->src[0] == SSA_FIXED_REGISTER(REGISTER_CONSTANT) &&
2731 mir_flip(ins);
2734 if (ins->src[1] == SSA_FIXED_REGISTER(REGISTER_CONSTANT)) {
2736 assert(ins->mask);
2737 unsigned first_comp = ffs(ins->mask) - 1;
2738 unsigned component = ins->swizzle[1][first_comp];
2744 scaled_constant = ins->constants.u16[component];
2746 scaled_constant = ins->constants.u32[component];
2749 if (scaled_constant != ins->constants.u32[component])
2752 float original = ins->constants.f32[component];
2769 if (ins->src_abs[1] || ins->src_neg[1])
2775 const midgard_constants *cons = &ins->constants;
2779 unsigned mask = effective_writemask(ins->op, ins->mask);
2787 cons->u16[ins->swizzle[1][c]] :
2788 cons->u32[ins->swizzle[1][c]];
2800 ins->has_constants = false;
2801 ins->src[1] = ~0;
2802 ins->has_inline_constant = true;
2803 ins->inline_constant = scaled_constant;
2816 mir_foreach_instr_in_block_safe(block, ins) {
2817 if (!midgard_is_branch_unit(ins->unit)) continue;
2820 mir_remove_instruction(ins);
2836 mir_foreach_instr_in_block(block, ins) {
2837 if (ins->type != TAG_ALU_4) continue;
2839 if (ins->op != midgard_alu_op_iand &&
2840 ins->op != midgard_alu_op_ior) continue;
2842 if (ins->src_invert[1] || !ins->src_invert[0]) continue;
2844 if (ins->has_inline_constant) {
2847 ins->inline_constant = ~ins->inline_constant;
2848 ins->src_invert[1] = true;
2853 mir_flip(ins);
2863 struct midgard_instruction ins = v_branch(false, false);
2864 ins.writeout = br->writeout;
2865 ins.branch.target_block = ctx->block_count - 1;
2866 ins.constants.u32[0] = br->constants.u32[0];
2867 memcpy(&ins.src_types, &br->src_types, sizeof(ins.src_types));
2868 emit_mir_instruction(ctx, ins);
2872 return ins.branch.target_block;
2998 mir_foreach_instr_in_block(((midgard_block *) _block), ins) {
2999 if (ins->type != TAG_ALU_4) continue;
3000 if (!ins->compact_branch) continue;
3003 if (ins->branch.target_type != TARGET_BREAK) continue;
3006 if (ins->branch.target_break != loop_idx) continue;
3011 ins->branch.target_type = TARGET_GOTO;
3012 ins->branch.target_block = break_block_idx;