Lines Matching defs:ins
228 mir_set_offset(compiler_context *ctx, midgard_instruction *ins, nir_src *offset, unsigned seg)
231 ins->swizzle[1][i] = 0;
232 ins->swizzle[2][i] = 0;
240 ins->load_store.bitsize_toggle = true;
241 ins->load_store.arg_comp = seg & 0x3;
242 ins->load_store.arg_reg = (seg >> 2) & 0x7;
243 ins->src[2] = nir_src_index(ctx, offset);
244 ins->src_types[2] = nir_type_uint | nir_src_bit_size(*offset);
247 ins->load_store.index_format = midgard_index_address_s32;
249 ins->load_store.index_format = midgard_index_address_u64;
262 ins->src[1] = nir_ssa_index(match.A.def);
263 ins->swizzle[1][0] = match.A.comp;
264 ins->src_types[1] = nir_type_uint | bitsize;
265 ins->load_store.bitsize_toggle = (bitsize == 64);
267 ins->load_store.bitsize_toggle = true;
268 ins->load_store.arg_comp = seg & 0x3;
269 ins->load_store.arg_reg = (seg >> 2) & 0x7;
273 ins->src[2] = nir_ssa_index(match.B.def);
274 ins->swizzle[2][0] = match.B.comp;
275 ins->src_types[2] = nir_type_uint | match.B.def->bit_size;
277 ins->load_store.index_reg = REGISTER_LDST_ZERO;
282 ins->load_store.index_format = match.type;
285 ins->load_store.index_shift = match.shift;
287 ins->constants.u32[0] = match.bias;
292 mir_set_ubo_offset(midgard_instruction *ins, nir_src *src, unsigned bias)
298 ins->src[2] = nir_ssa_index(match.B.def);
300 for (unsigned i = 0; i < ARRAY_SIZE(ins->swizzle[2]); ++i)
301 ins->swizzle[2][i] = match.B.comp;
304 ins->load_store.index_shift = match.shift;
305 ins->constants.u32[0] = match.bias + bias;