Lines Matching refs:src
521 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
525 mir_print_constant_component(fp, consts, src->component,
526 src->full ?
528 false, src->mod, alu->op);
536 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
537 bool expands = INPUT_EXPANDS(src->expand_mode);
558 unsigned c = (src->swizzle >> (i * 2)) & 3;
563 switch (src->expand_mode) {
587 unsigned base = (src->swizzle >> (index * 2)) & 3;
590 switch (src->expand_mode) {
618 expands, src->mod, alu->op);
650 midgard_vector_alu_src *src = (midgard_vector_alu_src *)&src_binary;
652 validate_expand_mode(src->expand_mode, mode);
656 print_vec_swizzle(fp, src->swizzle, src->expand_mode, mode, src_mask);
660 print_srcmod(fp, is_int, INPUT_EXPANDS(src->expand_mode), src->mod, false);
878 midgard_scalar_alu_src *src = (midgard_scalar_alu_src *)&src_binary;
882 unsigned c = src->component;
884 if (src->full) {
891 print_srcmod(fp, is_int, !src->full, src->mod, true);
1380 /* src/dest register */
1385 /* Some opcodes don't have a swizzable src register, and
1456 /* src reg for reg2reg ldst opcodes */
1466 unsigned src = (word->swizzle >> 2) & 0x7;
1469 print_ldst_read_reg(fp, src);