Lines Matching refs:info
44 struct pan_shader_info *info);
48 pan_shader_stage(const struct pan_shader_info *info)
50 switch (info->stage) {
72 pan_depth_source(const struct pan_shader_info *info)
74 return info->fs.writes_depth ? MALI_DEPTH_SOURCE_SHADER :
81 pan_shader_prepare_midgard_rsd(const struct pan_shader_info *info,
84 assert((info->push.count & 3) == 0);
86 rsd->properties.uniform_count = info->push.count / 4;
87 rsd->properties.shader_has_side_effects = info->writes_global;
92 if (info->stage != MESA_SHADER_FRAGMENT) {
93 rsd->properties.work_register_count = info->work_reg_count;
96 info->fs.outputs_read;
100 info->fs.early_fragment_tests;
170 pan_shader_prepare_bifrost_rsd(const struct pan_shader_info *info,
173 unsigned fau_count = DIV_ROUND_UP(info->push.count, 2);
178 pan_register_allocation(info->work_reg_count);
181 pan_make_preload(info->stage, info->preload, &rsd->preload);
183 if (info->stage == MESA_SHADER_FRAGMENT) {
185 info->fs.writes_coverage || info->fs.can_discard;
188 !info->writes_global;
191 rsd->properties.shader_wait_dependency_6 = info->bifrost.wait_6;
192 rsd->properties.shader_wait_dependency_7 = info->bifrost.wait_7;
194 pan_pack_message_preload(&rsd->message_preload_1, &info->bifrost.messages[0]);
195 pan_pack_message_preload(&rsd->message_preload_2, &info->bifrost.messages[1]);
197 } else if (info->stage == MESA_SHADER_VERTEX && info->vs.secondary_enable) {
200 pan_make_preload(info->stage, info->vs.secondary_preload,
204 info->vs.secondary_offset;
208 pan_register_allocation(info->vs.secondary_work_reg_count);