Lines Matching refs:src
69 ASSERTED bi_index lo = I->src[s], hi = I->src[s + 1];
135 bi_index idx = I->src[s];
451 /* First src is staging if we read, skip it when packing sources */
460 bi_index src = I->src[logical_i + src_offset];
464 if (src.neg) hex |= (1ull << 35);
469 if (src.neg) hex |= 1ull << neg_offs;
470 if (src.abs) hex |= 1ull << abs_offs;
472 if (src.neg) invalid_instruction(I, "negate");
473 if (src.abs) invalid_instruction(I, "absolute value");
478 unsigned S = src.swizzle;
485 hex |= (uint64_t) va_pack_widen(I, src.swizzle, src_info.size) << offs;
492 hex |= (src.swizzle == BI_SWIZZLE_H11 ? 1 : 0) << offs;
494 hex |= ((uint64_t) va_pack_combine(I, src.swizzle) << 37);
497 unsigned comp = src.swizzle - BI_SWIZZLE_B0000;
504 hex |= (uint64_t) va_pack_shift_lanes(I, src.swizzle) << 26;
509 hex |= (uint64_t) va_pack_widen_f32(I, src.swizzle) << 37;
513 hex |= (uint64_t) va_pack_halfswizzle(I, src.swizzle) << 36;
514 } else if (src.swizzle != BI_SWIZZLE_H01) {
664 bi_index sr = read ? I->src[0] : I->dest[0];
768 hex |= ((uint64_t) va_pack_reg(I, I->src[1])) << 16;
924 bi_branchzi(&b, va_zero_lut(), I->src[3], BI_CMPF_EQ);