Lines Matching refs:src
221 for i, (op, src) in enumerate(zip(operands, ins.srcs)):
233 if mod in src.offset and src.bits[mod] == 1:
234 encoded |= (1 << src.offset[mod])
235 elif src.halfswizzle and mod in enums[f'half_swizzles_{src.size}_bit'].bare_values:
238 val = enums[f'half_swizzles_{src.size}_bit'].bare_values.index(mod)
239 encoded |= (val << src.offset['widen'])
240 elif mod in enums[f'swizzles_{src.size}_bit'].bare_values and (src.widen or src.lanes):
243 val = enums[f'swizzles_{src.size}_bit'].bare_values.index(mod)
244 encoded |= (val << src.offset['widen'])
245 elif src.lane and mod in enums[f'lane_{src.size}_bit'].bare_values:
248 val = enums[f'lane_{src.size}_bit'].bare_values.index(mod)
249 encoded |= (val << src.offset['lane'])
250 elif src.combine and mod in enums['combine'].bare_values:
254 encoded |= (val << src.offset['combine'])
255 elif src.size == 32 and mod in enums['widen'].bare_values:
256 die_if(not src.swizzle, "Instruction doesn't take widens")
260 encoded |= (val << src.offset['swizzle'])
261 elif src.size == 16 and mod in enums['swizzles_16_bit'].bare_values:
262 die_if(not src.swizzle, "Instruction doesn't take swizzles")
266 encoded |= (val << src.offset['swizzle'])
268 die_if(not src.lane, "Instruction doesn't take a lane")
272 encoded |= (val << src.lane)
274 die_if(not src.lanes, "Instruction doesn't take a lane")
278 encoded |= (val << src.offset['widen'])
291 if src.swizzle and not swizzled and src.size == 16:
294 encoded |= (val << src.offset['swizzle'])
295 elif src.widen and not swizzled and src.size == 16:
299 encoded |= (val << src.offset['widen'])
301 encoded |= encoded_src << src.start