Lines Matching refs:info
526 /* Gather info as we go */
527 b->shader->info.bifrost->uses_flat_shading = true;
668 b->shader->nir->info.num_ubos;
671 b->shader->info.sysvals,
803 b->shader->info.bifrost->blend[rt].type = T;
806 b->shader->info.bifrost->blend_src1_type = T2;
1389 util_bitcount64(ctx->nir->info.inputs_read) : 0;
1880 assert(b->shader->nir->info.has_transform_feedback_varyings);
4113 for (unsigned i = 0; i < ARRAY_SIZE(ctx->info.bifrost->messages); ++i) {
4114 struct bifrost_message_preload msg = ctx->info.bifrost->messages[i];
4176 bool full_threads = (ctx->arch == 7 && ctx->info.work_reg_count <= 32);
4184 ctx->nir->info.label ?: "",
4238 unsigned nr_threads = (ctx->info.work_reg_count <= 32) ? 2 : 1;
4245 ctx->nir->info.label ?: "",
4353 * keep divergence info around after we consume it for indirect lowering,
4540 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
4557 * gathered info to skip the extra analysis in the happy path. */
4559 nir->info.inputs_read_indirectly ||
4560 nir->info.outputs_accessed_indirectly ||
4561 nir->info.patch_inputs_read_indirectly ||
4562 nir->info.patch_outputs_accessed_indirectly ||
4563 nir->info.images_used[0];
4757 ctx->info.bifrost->wait_6 = (first_deps & (1 << 6));
4758 ctx->info.bifrost->wait_7 = (first_deps & (1 << 7));
4829 assert(nir->info.stage == MESA_SHADER_FRAGMENT);
4850 if (nir->info.stage == MESA_SHADER_VERTEX) {
4891 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
4914 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
4921 if (nir->xfb_info != NULL && nir->info.has_transform_feedback_varyings) {
4936 struct bi_shader_info info,
4947 ctx->stage = nir->info.stage;
4950 ctx->info = info;
4988 bool skip_internal = nir->info.internal;
5193 struct pan_shader_info *info,
5197 .push = &info->push,
5198 .bifrost = &info->bifrost,
5199 .tls_size = info->tls_size,
5200 .sysvals = &info->sysvals,
5201 .push_offset = info->push.count
5235 if (nir->info.stage == MESA_SHADER_FRAGMENT && ctx->arch >= 9)
5238 info->ubo_mask |= ctx->ubo_mask;
5239 info->tls_size = MAX2(info->tls_size, ctx->info.tls_size);
5242 info->vs.secondary_enable = (binary->size > offset);
5243 info->vs.secondary_offset = offset;
5244 info->vs.secondary_preload = preload;
5245 info->vs.secondary_work_reg_count = ctx->info.work_reg_count;
5247 info->preload = preload;
5248 info->work_reg_count = ctx->info.work_reg_count;
5252 !nir->info.internal &&
5253 nir->info.outputs_written & BITFIELD_BIT(VARYING_SLOT_PSIZ)) {
5275 info->vs.no_psiz_offset = binary->size;
5291 if (nir->info.stage != MESA_SHADER_VERTEX)
5296 nir->info.outputs_written & BITFIELD_BIT(VARYING_SLOT_PSIZ))
5307 struct pan_shader_info *info)
5313 panfrost_init_sysvals(&info->sysvals,
5317 info->tls_size = nir->scratch_size;
5318 info->vs.idvs = bi_should_idvs(nir, inputs);
5320 if (info->vs.idvs) {
5321 bi_compile_variant(nir, inputs, binary, sysval_to_id, info, BI_IDVS_POSITION);
5322 bi_compile_variant(nir, inputs, binary, sysval_to_id, info, BI_IDVS_VARYING);
5324 bi_compile_variant(nir, inputs, binary, sysval_to_id, info, BI_IDVS_NONE);
5327 if (gl_shader_stage_is_compute(nir->info.stage)) {
5333 info->cs.allow_merging_workgroups =
5334 (nir->info.shared_size == 0) &&
5335 !nir->info.uses_control_barrier &&
5336 !nir->info.uses_memory_barrier;
5339 info->ubo_mask &= (1 << nir->info.num_ubos) - 1;