Lines Matching defs:load
1530 // propagate the add bit into an indirect load.
2728 Record *findRecord(const Instruction *, bool load, bool& isAdjacent) const;
2730 // merge @insn into load/store instruction from @rec
2797 // lock any stores that overlap with the load being merged into the
2867 // remove any existing load/store records for the store being merged into
2962 MemoryOpt::findRecord(const Instruction *insn, bool load, bool& isAdj) const
2967 Record *it = load ? loads[sym->reg.file] : stores[sym->reg.file];
3245 // or combine a previous load with this one
3972 // Each load can go into up to 4 destinations, any of which might potentially
3975 // the first load, and then put the second contiguous region into the second
3976 // load. There can be at most 2 contiguous regions.
3979 // a 64-bit load that's not 64-bit aligned, so such a load has to be split
3981 // split into a 64-bit and 32-bit load.
4003 // Compute address/width for first load
4018 // Scale back the size of the first load until it can be loaded. This
4027 // Compute address/width for second load
4082 RUN_PASS(2, ModifierFolding, run); // before load propagation -> less checks