Lines Matching defs:nir
202 nir_shader **nir)
205 *nir = vk_pipeline_cache_lookup_nir(cache, hash, SHA1_DIGEST_LENGTH,
207 if (*nir)
231 &spirv_opts, nir_opts, NULL, nir);
255 dxil_spirv_nir_passes(*nir, &conf, &requires_runtime_data);
265 NIR_PASS_V(*nir, dxil_nir_lower_vs_vertex_conversion, vi_conversions);
269 vk_pipeline_cache_add_nir(cache, hash, SHA1_DIGEST_LENGTH, *nir);
343 nir_shader *nir,
359 nir_print_shader(nir, stderr);
361 if (nir_to_dxil(nir, &opts, &dxil_blob)) {
799 &nir_opts, &pipeline->templates.shaders[stage].nir);
813 assert(pipeline->templates.shaders[stage].nir);
814 dxil_spirv_nir_link(pipeline->templates.shaders[stage].nir,
816 pipeline->templates.shaders[prev_stage].nir : NULL);
822 NIR_PASS_V(pipeline->templates.shaders[stage].nir, adjust_var_bindings, layout,
864 if (pipeline->templates.shaders[MESA_SHADER_VERTEX].nir) {
868 nir_foreach_shader_in_variable(var, pipeline->templates.shaders[MESA_SHADER_VERTEX].nir) {
899 !(pipeline->templates.shaders[prev_stage].nir->info.outputs_written & VARYING_BIT_POS))
906 ret = dzn_pipeline_compile_shader(device, pipeline->templates.shaders[stage].nir, slot);
1563 ralloc_free(pipeline->templates.shaders[i].nir);
1564 pipeline->templates.shaders[i].nir = NULL;
2084 nir_shader *nir = NULL;
2108 dxil_get_nir_compiler_options(), &nir);
2114 NIR_PASS_V(nir, adjust_var_bindings, layout, cache ? bindings_hash : NULL);
2139 ret = dzn_pipeline_compile_shader(device, nir, shader);
2152 ralloc_free(nir);