Lines Matching defs:device
101 vk_free(&shader->base.device->alloc, shader);
105 dzn_cached_blob_create(struct vk_device *device,
111 dzn_cached_blob_deserialize(struct vk_device *device,
119 return dzn_cached_blob_create(device, key_data,
132 dzn_cached_blob_create(struct vk_device *device,
141 if (!vk_multialloc_alloc(&ma, &device->alloc,
147 vk_pipeline_cache_object_init(device, &blob->base,
160 dzn_graphics_pipeline_prepare_for_variants(struct dzn_device *device,
171 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
191 dzn_pipeline_get_nir_shader(struct dzn_device *device,
229 vk_shader_module_to_nir(&device->vk, module, stage,
342 dzn_pipeline_compile_shader(struct dzn_device *device,
347 container_of(device->vk.physical->instance, struct dzn_instance, vk);
365 result = vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
403 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
480 ret = vk_error(cache->base.device, VK_ERROR_OUT_OF_HOST_MEMORY);
505 dzn_cached_blob_create(cache->base.device, dxil_hash, NULL, size);
616 dzn_cached_blob_create(cache->base.device, pipeline_hash, NULL, offset);
663 dzn_graphics_pipeline_compile_shaders(struct dzn_device *device,
792 ret = dzn_pipeline_get_nir_shader(device, layout,
906 ret = dzn_pipeline_compile_shader(device, pipeline->templates.shaders[stage].nir, slot);
1061 dzn_graphics_pipeline_translate_ia(struct dzn_device *device,
1091 ret = dzn_graphics_pipeline_prepare_for_variants(device, pipeline);
1509 struct dzn_device *device,
1528 vk_object_base_init(&device->vk, &pipeline->base, VK_OBJECT_TYPE_PIPELINE);
1598 vk_free2(&pipeline->base.base.device->alloc, alloc, pipeline);
1602 dzn_graphics_pipeline_create(struct dzn_device *device,
1620 vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
1623 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
1628 dzn_pipeline_init(&pipeline->base, device,
1665 ret = dzn_graphics_pipeline_prepare_for_variants(device, pipeline);
1677 ret = dzn_graphics_pipeline_translate_ia(device, pipeline, stream_desc, pCreateInfo);
1737 ret = dzn_graphics_pipeline_compile_shaders(device, pipeline, pcache,
1745 hres = ID3D12Device2_CreatePipelineState(device->dev, stream_desc,
1749 ret = vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
1799 struct dzn_device *device =
1800 container_of(pipeline->base.base.device, struct dzn_device, vk);
1862 ASSERTED HRESULT hres = ID3D12Device2_CreatePipelineState(device->dev, &stream_desc,
1890 struct dzn_device *device =
1891 container_of(pipeline->base.base.device, struct dzn_device, vk);
1945 ID3D12Device1_CreateCommandSignature(device->dev, &cmd_sig_desc,
1964 VK_FROM_HANDLE(dzn_device, device, dev);
1969 result = dzn_graphics_pipeline_create(device,
2005 vk_free2(&pipeline->base.base.device->alloc, alloc, pipeline);
2060 dzn_cached_blob_create(cache->base.device, pipeline_hash, NULL, SHA1_DIGEST_LENGTH);
2074 dzn_compute_pipeline_compile_shader(struct dzn_device *device,
2104 ret = dzn_pipeline_get_nir_shader(device, layout, cache, spirv_hash,
2139 ret = dzn_pipeline_compile_shader(device, nir, shader);
2157 dzn_compute_pipeline_create(struct dzn_device *device,
2167 vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
2170 return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
2177 dzn_pipeline_init(&pipeline->base, device,
2183 dzn_compute_pipeline_compile_shader(device, pipeline, pcache, layout,
2188 if (FAILED(ID3D12Device2_CreatePipelineState(device->dev, &stream_desc,
2191 ret = vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
2209 struct dzn_device *device =
2210 container_of(pipeline->base.base.device, struct dzn_device, vk);
2233 ID3D12Device1_CreateCommandSignature(device->dev, &indirect_dispatch_desc,
2251 VK_FROM_HANDLE(dzn_device, device, dev);
2256 result = dzn_compute_pipeline_create(device,
2282 dzn_DestroyPipeline(VkDevice device,