Lines Matching defs:cache
193 struct vk_pipeline_cache *cache,
204 if (cache) {
205 *nir = vk_pipeline_cache_lookup_nir(cache, hash, SHA1_DIGEST_LENGTH,
268 if (cache)
269 vk_pipeline_cache_add_nir(cache, hash, SHA1_DIGEST_LENGTH, *nir);
446 dzn_pipeline_cache_lookup_dxil_shader(struct vk_pipeline_cache *cache,
453 if (!cache)
459 vk_pipeline_cache_lookup_object(cache, dxil_hash, SHA1_DIGEST_LENGTH,
480 ret = vk_error(cache->base.device, VK_ERROR_OUT_OF_HOST_MEMORY);
496 dzn_pipeline_cache_add_dxil_shader(struct vk_pipeline_cache *cache,
505 dzn_cached_blob_create(cache->base.device, dxil_hash, NULL, size);
517 cache_obj = vk_pipeline_cache_add_object(cache, cache_obj);
528 struct vk_pipeline_cache *cache,
534 if (!cache)
540 vk_pipeline_cache_lookup_object(cache, pipeline_hash, SHA1_DIGEST_LENGTH,
582 dzn_pipeline_cache_lookup_dxil_shader(cache, dxil_hash, &stage, slot);
598 struct vk_pipeline_cache *cache,
616 dzn_cached_blob_create(cache->base.device, pipeline_hash, NULL, offset);
645 cache_obj = vk_pipeline_cache_add_object(cache, cache_obj);
665 struct vk_pipeline_cache *cache,
743 if (cache) {
763 ret = dzn_pipeline_cache_lookup_gfx_pipeline(pipeline, cache, pipeline_hash,
779 if (cache) {
793 cache, nir_hash,
823 cache ? bindings_hash : NULL);
825 if (cache) {
849 ret = dzn_pipeline_cache_lookup_dxil_shader(cache, stages[stage].dxil_hash, &cached_stage, &bc);
912 if (cache)
913 dzn_pipeline_cache_add_dxil_shader(cache, stages[stage].dxil_hash, stage, slot);
916 if (cache)
917 dzn_pipeline_cache_add_gfx_pipeline(pipeline, cache, vert_input_count, pipeline_hash,
1603 VkPipelineCache cache,
1610 VK_FROM_HANDLE(vk_pipeline_cache, pcache, cache);
2009 dzn_pipeline_cache_lookup_compute_pipeline(struct vk_pipeline_cache *cache,
2017 if (!cache)
2023 vk_pipeline_cache_lookup_object(cache, pipeline_hash, SHA1_DIGEST_LENGTH,
2038 dzn_pipeline_cache_lookup_dxil_shader(cache, dxil_hash, &stage, dxil);
2055 dzn_pipeline_cache_add_compute_pipeline(struct vk_pipeline_cache *cache,
2060 dzn_cached_blob_create(cache->base.device, pipeline_hash, NULL, SHA1_DIGEST_LENGTH);
2069 cache_obj = vk_pipeline_cache_add_object(cache, cache_obj);
2076 struct vk_pipeline_cache *cache,
2086 if (cache) {
2097 ret = dzn_pipeline_cache_lookup_compute_pipeline(cache, pipeline_hash,
2104 ret = dzn_pipeline_get_nir_shader(device, layout, cache, spirv_hash,
2114 NIR_PASS_V(nir, adjust_var_bindings, layout, cache ? bindings_hash : NULL);
2116 if (cache) {
2126 ret = dzn_pipeline_cache_lookup_dxil_shader(cache, dxil_hash, &stage, shader);
2134 dzn_pipeline_cache_add_compute_pipeline(cache, pipeline_hash, dxil_hash);
2146 if (cache) {
2147 dzn_pipeline_cache_add_dxil_shader(cache, dxil_hash, MESA_SHADER_COMPUTE, shader);
2148 dzn_pipeline_cache_add_compute_pipeline(cache, pipeline_hash, dxil_hash);
2158 VkPipelineCache cache,
2164 VK_FROM_HANDLE(vk_pipeline_cache, pcache, cache);