Lines Matching defs:shader
50 { "dump_blob", DXIL_DEBUG_DUMP_BLOB , "Write shader blobs" },
184 unreachable("invalid shader kind");
450 struct nir_shader *shader;
1000 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_mem_ssbo)
1162 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_shader_temp) {
1353 const nir_shader *s = ctx->shader;
1417 hs_state_nodes[2] = dxil_get_metadata_int32(&ctx->mod, ctx->shader->info.tess.tcs_vertices_out);
1418 hs_state_nodes[3] = dxil_get_metadata_int32(&ctx->mod, get_tessellator_domain(ctx->shader->info.tess._primitive_mode));
1419 hs_state_nodes[4] = dxil_get_metadata_int32(&ctx->mod, get_tessellator_partitioning(ctx->shader->info.tess.spacing));
1420 hs_state_nodes[5] = dxil_get_metadata_int32(&ctx->mod, get_tessellator_output_primitive(&ctx->shader->info));
1431 ds_state_nodes[0] = dxil_get_metadata_int32(&ctx->mod, get_tessellator_domain(ctx->shader->info.tess._primitive_mode));
1432 ds_state_nodes[1] = dxil_get_metadata_int32(&ctx->mod, ctx->shader->info.tess.tcs_vertices_out);
1440 const nir_shader *s = ctx->shader;
1456 * https://github.com/Microsoft/DirectXShaderCompiler/blob/master/docs/DXIL.rst#shader-flags
1462 if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT &&
1463 ctx->shader->info.fs.early_fragment_tests)
1576 /* DXIL versions are 1.x for shader model 6.x */
1619 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_shader_in) {
1649 nir_function_impl *entry_func_impl = nir_shader_get_entrypoint(ctx->shader);
2763 unsigned num_coords = ctx->shader->info.tess._primitive_mode == TESS_PRIMITIVE_TRIANGLES ? 3 : 2;
2901 nir_variable *var = nir_get_binding_variable(ctx->shader, nir_chase_binding(intr->src[0]));
3195 nir_variable *var = find_patch_matching_variable_by_driver_location(ctx->shader, nir_var_shader_out, nir_intrinsic_base(intr), is_patch_constant);
3253 nir_variable *var = nir_find_variable_with_driver_location(ctx->shader, nir_var_shader_in, nir_intrinsic_base(intr));
3337 nir_variable *var = find_patch_matching_variable_by_driver_location(ctx->shader, nir_var_shader_in, nir_intrinsic_base(intr), is_patch_constant);
3438 nir_variable *var = find_patch_matching_variable_by_driver_location(ctx->shader, nir_var_shader_in, nir_intrinsic_base(intr), false);
3918 nir_variable *var = nir_get_binding_variable(ctx->shader, nir_chase_binding(intr->src[0]));
4122 nir_variable *var = nir_get_binding_variable(ctx->shader, nir_chase_binding(intr->src[0]));
4257 unreachable("Unexpected shader kind for invocation ID");
5205 * on the fly while loading. So scan the shader and insert a typed dummy
5229 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_mem_ubo) {
5234 if (ctx->shader->info.num_ubos) {
5238 unsigned ubo1_array_size = ctx->shader->info.num_ubos -
5248 !emit_cbv(ctx, ctx->shader->info.num_ubos - 1, 0, ubo_size, 1, "__ubo_state_vars"))
5259 if (ctx->shader->scratch_size) {
5266 unsigned size = ALIGN_POT(ctx->shader->scratch_size, sizeof(uint32_t));
5381 sort_uniforms_by_binding_and_remove_structs(ctx->shader);
5388 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_uniform) {
5396 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_uniform) {
5403 nir_foreach_image_variable(var, ctx->shader) {
5412 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_mem_ssbo) {
5423 if (ctx->shader->info.shared_size && shader_has_shared_ops(ctx->shader)) {
5437 size = ALIGN_POT(ctx->shader->info.shared_size, sizeof(uint32_t));
5448 if (ctx->shader->info.stage == MESA_SHADER_KERNEL) {
5459 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_mem_ssbo) {
5472 for (unsigned i = 0; i < ctx->shader->info.num_ssbos; ++i) {
5481 * for dynamic indexing. Space 0 will be individual SSBOs in the DXIL shader, while
5484 if (ctx->shader->info.num_ssbos &&
5485 !emit_uav(ctx, 0, 2, ctx->shader->info.num_ssbos, DXIL_COMP_TYPE_INVALID,
5490 nir_foreach_image_variable(var, ctx->shader) {
5500 BITSET_TEST(ctx->shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID);
5501 if (!ctx->mod.info.has_per_sample_input && ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
5502 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_shader_in | nir_var_system_value) {
5511 ctx->shader->info.clip_distance_array_size : ctx->opts->input_clip_size;
5512 preprocess_signatures(&ctx->mod, ctx->shader, input_clip_size);
5514 nir_foreach_function(func, ctx->shader) {
5519 if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
5520 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_shader_out) {
5525 } else if (ctx->shader->info.stage == MESA_SHADER_VERTEX ||
5526 ctx->shader->info.stage == MESA_SHADER_TESS_EVAL) {
5527 if (ctx->shader->info.outputs_written &
5557 unreachable("unknown shader stage in nir_to_dxil");
5652 state->state.num_threads_x = MAX2(ctx->shader->info.workgroup_size[0], 1);
5653 state->state.num_threads_y = MAX2(ctx->shader->info.workgroup_size[1], 1);
5654 state->state.num_threads_z = MAX2(ctx->shader->info.workgroup_size[2], 1);
5657 state->state.psv1.max_vertex_count = ctx->shader->info.gs.vertices_out;
5658 state->state.psv1.psv0.gs.input_primitive = dxil_get_input_primitive(ctx->shader->info.gs.input_primitive);
5659 state->state.psv1.psv0.gs.output_toplology = dxil_get_primitive_topology(ctx->shader->info.gs.output_primitive);
5660 state->state.psv1.psv0.gs.output_stream_mask = MAX2(ctx->shader->info.gs.active_stream_mask, 1);
5665 state->state.psv1.psv0.hs.output_control_point_count = ctx->shader->info.tess.tcs_vertices_out;
5666 state->state.psv1.psv0.hs.tessellator_domain = get_tessellator_domain(ctx->shader->info.tess._primitive_mode);
5667 state->state.psv1.psv0.hs.tessellator_output_primitive = get_tessellator_output_primitive(&ctx->shader->info);
5671 state->state.psv1.psv0.ds.input_control_point_count = ctx->shader->info.tess.tcs_vertices_out;
5672 state->state.psv1.psv0.ds.tessellator_domain = get_tessellator_domain(ctx->shader->info.tess._primitive_mode);
5687 nir_variable *var = rzalloc(ctx->shader, nir_variable);
5707 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_shader_in) {
5719 nir_shader_add_variable(ctx->shader, ctx->system_value[sv_slot]);
5740 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_shader_in)
5742 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_system_value)
5745 if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT &&
5746 ctx->shader->info.inputs_read &&
5747 !BITSET_TEST(ctx->shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID)) {
5756 nir_foreach_variable_with_modes(var, ctx->shader, nir_var_shader_in) {
5764 BITSET_SET(ctx->shader->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID);
5770 info->only_in_shader != ctx->shader->info.stage)
5772 if (BITSET_TEST(ctx->shader->info.system_values_read, info->value)) {
5808 debug_printf("D3D12: cannot support emitting shader model 6.0 or lower\n");
5833 ctx->shader = s;
5906 debug_printf("D3D12: max shader model exceeded\n");
5913 debug_printf("D3D12: shader model exceeds max that can be validated\n");