Lines Matching defs:data

947       const struct dxil_resource_v0 *resource = (const struct dxil_resource_v0 *)((const char *)ctx->resources.data + resource_element_size * i);
963 unsigned binding = var->data.binding;
964 resource_array_layout layout = {id, binding, count, var->data.descriptor_set};
969 if (var->data.mode == nir_var_mem_ssbo) {
1075 binding = var->data.driver_location;
1078 binding = var->data.binding;
1079 space = var->data.descriptor_set;
1247 return emit_cbv(ctx, var->data.binding, var->data.descriptor_set,
1255 unsigned binding = var->data.binding;
1256 resource_array_layout layout = {id, binding, count, var->data.descriptor_set};
1286 for (struct dxil_resource_v0 *res = (struct dxil_resource_v0 *)ctx->resources.data;
1287 res < (struct dxil_resource_v0 *)((char *)ctx->resources.data + ctx->resources.size);
1531 #define ARRAY_AND_SIZE(arr) arr.data, util_dynarray_num_elements(&arr, const struct dxil_mdnode *)
2801 assert(var->data.mode == nir_var_shader_temp);
2805 const struct dxil_value *ptr = he->data;
2902 if (var && var->data.access & ACCESS_NON_WRITEABLE)
3149 if (var->data.driver_location == driver_location &&
3150 var->data.patch == patch)
3196 unsigned var_base_component = var->data.location_frac;
3255 attr_at_vertex = var && var->data.interpolation == INTERP_MODE_FLAT;
3338 unsigned var_base_component = var ? var->data.location_frac : 0;
3439 unsigned var_base_component = var ? var->data.location_frac : 0;
3919 if (var && var->data.access & ACCESS_NON_WRITEABLE)
4132 if (var->data.access & ACCESS_NON_WRITEABLE)
4471 var->data.driver_location : var->data.binding;
4503 (var->data.access & ACCESS_NON_WRITEABLE))
4514 var->data.descriptor_set : (glsl_type_is_image(type) ? 1 : 0);
5176 if (var->data.binding > new_var->data.binding) {
5362 (struct phi_block *)entry->data))
5404 if ((var->data.access & ACCESS_NON_WRITEABLE) &&
5413 if ((var->data.access & ACCESS_NON_WRITEABLE) != 0) {
5460 if ((var->data.access & ACCESS_NON_WRITEABLE) == 0) {
5464 if (!emit_uav(ctx, var->data.binding, var->data.descriptor_set,
5492 var && (var->data.access & ACCESS_NON_WRITEABLE))
5503 if (var->data.sample) {
5521 if (var->data.location == FRAG_RESULT_STENCIL) {
5563 lower_bit_size_callback(const nir_instr* instr, void *data)
5573 const struct nir_to_dxil_options *opts = (const struct nir_to_dxil_options*)data;
5634 state->resources.v0 = (struct dxil_resource_v0*)ctx->resources.data;
5690 var->data.driver_location = driver_location;
5691 var->data.location = value;
5694 var->data.mode = nir_var_system_value;
5695 var->data.interpolation = INTERP_MODE_FLAT;
5708 if (var->data.location == input_loc) {
5750 /* "var->data.sample = true" sometimes just mean, "I want per-sample
5757 if (!var->data.sample || var->data.interpolation != INTERP_MODE_FLAT) {
5999 fwrite(blob->data, 1, blob->size, f);
6014 switch (var->data.location) {
6026 if (!((1ull << var->data.location) & other_stage_mask))